Test Coverage Report for Board: 80-MB0M80-A01 _______________________________________________________________________ Non-MDA Test Coverage ___________________________ Name Location Pins PWR/NC Testable Tested % Comment ____________________________________________________________________________________________________ UL1T1 Loc:C1 Side:T 24 4 20 9 45.0 UL1U1 Loc:B1 Side:T 37 8 29 8 27.6 UF1U1 Loc:B4 Side:T 8 2 6 5 83.3 UBU3 Loc:A1 Side:T 20 2 18 0 0.0 U31P1 Loc:C2 Side:T 13 8 5 0 0.0 U31P3 Loc:C2 Side:T 13 8 5 0 0.0 U31U1 Loc:C1 Side:T 8 4 4 0 0.0 U31U5 Loc:D1 Side:T 29 16 13 0 0.0 U31U6 Loc:C1 Side:T 14 2 12 8 66.7 U3CP1 Loc:C1 Side:T 8 3 5 2 40.0 U3CP2 Loc:C1 Side:T 8 3 5 0 0.0 U3U1 Loc:D1 Side:T 77 28 49 0 0.0 UAU1 Loc:A1 Side:T 48 13 35 25 71.4 UDIA1 Loc:D4 Side:T 242 73 169 0 0.0 UDIA2 Loc:D4 Side:T 242 72 170 0 0.0 UDIB1 Loc:D4 Side:T 242 72 170 0 0.0 UDIB2 Loc:D4 Side:T 242 71 171 0 0.0 UGU1 Loc:E1 Side:T 38 12 26 3 11.5 UGU2 Loc:E1 Side:T 53 23 30 11 36.7 UK1U1 Loc:B2 Side:T 128 42 86 61 70.9 ULGA1 Loc:D3 Side:T 1151 418 733 0 0.0 UO2U1 Loc:C3 Side:T 21 8 13 0 0.0 UOU1 Loc:B1 Side:T 64 4 60 42 70.0 UO310 Loc:F4 Side:T 18 15 3 2 66.7 UO320 Loc:B1 Side:T 18 15 3 2 66.7 UPCI1 Loc:B2 Side:T 122 26 96 0 0.0 UPEX1 Loc:C2 Side:T 166 71 95 0 0.0 UPEX2 Loc:A2 Side:T 101 40 61 0 0.0 UPCX1 Loc:B2 Side:T 38 12 26 0 0.0 UP101 Loc:F3 Side:T 57 6 51 43 84.3 UP102 Loc:F2 Side:T 11 5 6 3 50.0 UP103 Loc:F2 Side:T 11 5 6 3 50.0 UP104 Loc:F2 Side:T 11 5 6 3 50.0 UP201 Loc:F3 Side:T 11 5 6 3 50.0 UP202 Loc:F2 Side:T 11 5 6 3 50.0 UP302 Loc:C3 Side:T 8 2 6 0 0.0 UP501 Loc:F4 Side:T 13 4 9 8 88.9 UP503 Loc:C4 Side:T 13 7 6 3 50.0 UP701 Loc:A4 Side:T 13 6 7 0 0.0 UP704 Loc:B4 Side:T 16 10 6 4 66.7 UP705 Loc:B4 Side:T 8 2 6 3 50.0 UP706 Loc:D2 Side:T 13 4 9 7 77.8 USU1 Loc:B3 Side:T 837 442 395 242 61.3 ____________________________________________________________________________________________________ Pin Coverage 4226 1583 2643 503 19.0 % Device Summary Devices Testable Tested Coverage 43 43 24 55.8 % ____________________________________________________________________________________________________ Test Coverage Report for Board: 80-MB0M80-A01 _______________________________________________________________________ Non-IC Test Coverage ___________________________ Name Location Pins PWR/NC Testable Tested % Comment ____________________________________________________________________________________________________ None ____________________________________________________________________________________________________ Pin Coverage 0 0 0 0 0.0 % Device Summary Devices Testable Tested Coverage 0 0 0 0.0 % ____________________________________________________________________________________________________ MDA Test Coverage ___________________________ | (Untestable Components) | CompType Total | NoComp NoNail Parallel | Testable Tested NoTest CoverageRate(%) __________________________________________________________________________________________ Jumper : 584 - ( 412 25 0 ) = 147 136 11 92.5 Resistor : 443 - ( 0 1 9 ) = 433 433 0 100.0 Capacitor : 970 - ( 490 109 206 ) = 165 162 3 98.2 Bead/Coil : 0 Diode : 62 - ( 25 0 0 ) = 37 37 0 100.0 Transistor : 158 - ( 52 0 0 ) = 106 106 0 100.0 FET : 0 Others : 0 __________________________________________________________________________________________ Total : 2217 - ( 979 135 215 ) = 888 874 14 98.4 Device Summary Devices Testable Tested Coverage 2217 888 874 98.4 % __________________________________________________________________________________________ Non-MDA Detailed Test Coverage ______________________________ #1 UL1T1 Loc:C1 Side:T TotalPin:24 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 L1_CTR GND 2 2 L1_MDI_N3 ** NOT TESTED ** 3 3 L1_MDI_P3 ** NOT TESTED ** 4 4 L1_CTR GND 5 5 L1_MDI_N2 ** NOT TESTED ** 6 6 L1_MDI_P2 ** NOT TESTED ** 7 7 L1_CTR GND 8 8 L1_MDI_N1 ** NOT TESTED ** 9 9 L1_MDI_P1 ** NOT TESTED ** 10 10 L1_CTR GND 11 11 L1_MDI_N0 ** NOT TESTED ** 12 12 L1_MDI_P0 ** NOT TESTED ** 13 13 L1_TR_P0 X 14 14 L1_TR_N0 X 15 15 L1_CMT3 ** NOT TESTED ** 16 16 L1_TR_P1 X 17 17 L1_TR_N1 X 18 18 L1_CMT2 ** NOT TESTED ** 19 19 L1_TR_P2 X 20 20 L1_TR_N2 X 21 21 L1_CMT1 ** NOT TESTED ** 22 22 L1_TR_P3 X 23 23 L1_TR_N3 X 24 24 L1_CMT0 X _____________________________________________________________________________________________________________________________________________________ Totals 4 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 45.0 Testable Pins = 20 UnTested Pins = 11 Analog Coverage = 45.0 Analog Tested Pins = 9 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #2 UL1U1 Loc:B1 Side:T TotalPin:37 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 L1_MDI_P0 ** NOT TESTED ** 2 2 L1_MDI_N0 ** NOT TESTED ** 3 3 +L1_1_0V ** NOT TESTED ** 4 4 L1_MDI_P1 ** NOT TESTED ** 5 5 L1_MDI_N1 ** NOT TESTED ** 6 6 L1_MDI_P2 ** NOT TESTED ** 7 7 L1_MDI_N2 ** NOT TESTED ** 8 8 +L1_1_0V ** NOT TESTED ** 9 9 L1_MDI_P3 ** NOT TESTED ** 10 10 L1_MDI_N3 ** NOT TESTED ** 11 11 +3VSB_LAN1 VCC 12 12 CLKREQ__LAN1_R X 13 13 S_X1_LAN1_TXP_C ** NOT TESTED ** 14 14 S_X1_LAN1_TXN_C ** NOT TESTED ** 15 15 CK_100M_LAN1P ** NOT TESTED ** 16 16 CK_100M_LAN1N ** NOT TESTED ** 17 17 S_X1_LAN1_RXP_C ** NOT TESTED ** 18 18 S_X1_LAN1_RXN_C ** NOT TESTED ** 19 19 S_PLTRST_ ** NOT TESTED ** 20 20 L1_ISOLATE_ ** NOT TESTED ** 21 21 S_WAKE__LAN1 X 22 22 +L1_1_0V ** NOT TESTED ** 23 23 +3VSB_LAN1 VCC 24 24 +L1_1_0V_VOUT ** NOT TESTED ** 25 25 L1_LINK1000__R X 26 26 L1_LINK100_ X 27 27 L1_ACTLEDN X 28 28 L1_XIN X 29 29 L1_XOUT X 30 30 +L1_1_0V ** NOT TESTED ** 31 31 L1_LREXT X 32 32 +3VSB_LAN1 VCC 33 33 GND GND 34 34 GND GND 35 35 GND GND 36 36 GND GND 37 37 GND GND _____________________________________________________________________________________________________________________________________________________ Totals 8 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 27.6 Testable Pins = 29 UnTested Pins = 21 Analog Coverage = 27.6 Analog Tested Pins = 8 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #3 UF1U1 Loc:B4 Side:T TotalPin:8 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 S_SPI_CS0_ ** NOT TESTED ** 2 2 F_SPI_MISO X 3 3 F_BIOS_WP_ X 4 4 GND GND 5 5 F_SPI_MOSI X 6 6 F_SPI_CLK X 7 7 F_SPI_HOLD_ X 8 8 +3V_SPI VCC _____________________________________________________________________________________________________________________________________________________ Totals 2 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 83.3 Testable Pins = 6 UnTested Pins = 1 Analog Coverage = 83.3 Analog Tested Pins = 5 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #4 UBU3 Loc:A1 Side:T TotalPin:20 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 +12V ** NOT TESTED ** 2 2 LS_COM1_DCD1_ ** NOT TESTED ** 3 3 LS_COM1_DSR1_ ** NOT TESTED ** 4 4 LS_COM1_RXD1 ** NOT TESTED ** 5 5 LS_COM1_RTS1_ ** NOT TESTED ** 6 6 LS_COM1_TXD1 ** NOT TESTED ** 7 7 LS_COM1_CTS1_ ** NOT TESTED ** 8 8 LS_COM1_DTR1_ ** NOT TESTED ** 9 9 LS_COM1_RI1_ ** NOT TESTED ** 10 10 -12V ** NOT TESTED ** 11 11 GND GND 12 12 O_COM1_RI1__Q ** NOT TESTED ** 13 13 O_COM1_DTR1_ ** NOT TESTED ** 14 14 O_COM1_CTS1_ ** NOT TESTED ** 15 15 O_COM1_TXD1 ** NOT TESTED ** 16 16 O_COM1_RTS1_ ** NOT TESTED ** 17 17 O_COM1_RXD1 ** NOT TESTED ** 18 18 O_COM1_DSR1_ ** NOT TESTED ** 19 19 O_COM1_DCD1_ ** NOT TESTED ** 20 20 +5V VCC _____________________________________________________________________________________________________________________________________________________ Totals 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 0.0 Testable Pins = 18 UnTested Pins = 18 Analog Coverage = 0.0 Analog Tested Pins = 0 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #5 U31P1 Loc:C2 Side:T TotalPin:13 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 N17940587 ** NOT TESTED ** 2 2 U31PU1_EN ** NOT TESTED ** 3 3 +2_22V_U3E1 ** NOT TESTED ** 4 4 +5V_U31PU1 VCC 5 5 NC_1795 NC 6 6 +1_2V_U3E1 ** NOT TESTED ** 7 7 U31_1V2_FB_20 ** NOT TESTED ** 8 8 GND GND 9 9 GND GND 10 10 GND GND 11 11 GND GND 12 12 GND GND 13 13 GND GND _____________________________________________________________________________________________________________________________________________________ Totals 7 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 0.0 Testable Pins = 5 UnTested Pins = 5 Analog Coverage = 0.0 Analog Tested Pins = 0 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #6 U31P3 Loc:C2 Side:T TotalPin:13 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 U31PU1_EN ** NOT TESTED ** 2 2 S_1142_PWRCUT ** NOT TESTED ** 3 3 +3V VCC 4 4 +5V_U31PU3 ** NOT TESTED ** 5 5 NC_1796 NC 6 6 +2_22V_U3E1 ** NOT TESTED ** 7 7 U31_2V22_FB_20 ** NOT TESTED ** 8 8 GND GND 9 9 GND GND 10 10 GND GND 11 11 GND GND 12 12 GND GND 13 13 GND GND _____________________________________________________________________________________________________________________________________________________ Totals 7 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 0.0 Testable Pins = 5 UnTested Pins = 5 Analog Coverage = 0.0 Analog Tested Pins = 0 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #7 U31U1 Loc:C1 Side:T TotalPin:8 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 U3E1_SPI_CS_ ** NOT TESTED ** 2 2 U3E1_SPI_SODI ** NOT TESTED ** 3 3 +3V VCC 4 4 GND GND 5 5 U3E1_SPI_SIDO ** NOT TESTED ** 6 6 U3E1_SPI_CLK ** NOT TESTED ** 7 7 +3V VCC 8 8 +3V VCC _____________________________________________________________________________________________________________________________________________________ Totals 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 0.0 Testable Pins = 4 UnTested Pins = 4 Analog Coverage = 0.0 Analog Tested Pins = 0 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #8 U31U5 Loc:D1 Side:T TotalPin:29 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 +3VSD_U3C1 VCC 2 2 S_U3TXDN6_R ** NOT TESTED ** 3 3 S_U3TXDP6_R ** NOT TESTED ** 4 4 U3C_U3TXDN2_R ** NOT TESTED ** 5 5 U3C_U3TXDP2_R ** NOT TESTED ** 6 6 U3E_U3RXDN2_R ** NOT TESTED ** 7 7 U3E_U3RXDP2_R ** NOT TESTED ** 8 8 U3C_U3RXDN2_R ** NOT TESTED ** 9 9 U3C_U3RXDP2_R ** NOT TESTED ** 10 10 GND GND 11 11 GND GND 12 12 +3VSD_U3C1 VCC 13 13 GND GND 14 14 +3VSD_U3C1 VCC 15 15 GND GND 16 16 U3C_U3RXDP1_R ** NOT TESTED ** 17 17 U3C_U3RXDN1_R ** NOT TESTED ** 18 18 GND GND 19 19 +3VSD_U3C1 VCC 20 20 U3C_U3TXDP1_R ** NOT TESTED ** 21 21 U3C_U3TXDN1_R ** NOT TESTED ** 22 22 GND GND 23 23 U3C1_SEL ** NOT TESTED ** 24 24 +3VSD_U3C1 VCC 25 25 +3VSD_U3C1 VCC 26 26 GND GND 27 27 +3VSD_U3C1 VCC 28 28 GND GND 29 29 GND GND _____________________________________________________________________________________________________________________________________________________ Totals 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 0.0 Testable Pins = 13 UnTested Pins = 13 Analog Coverage = 0.0 Analog Tested Pins = 0 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #9 U31U6 Loc:C1 Side:T TotalPin:14 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 U3C1_DFP_CC1_O X 2 2 U3C1_DFP_CC1 ** NOT TESTED ** 3 3 U3C1_DFP_CC1_HREF X 4 4 +5VSB_DUAL VCC 5 5 U3C1_DFP_CC1_LREF X 6 6 U3C1_DFP_CC1 ** NOT TESTED ** 7 7 U3C1_O7 X 8 8 U3C1_O8 X 9 9 U3C1_DFP_CC2 ** NOT TESTED ** 10 10 U3C1_DFP_CC2_LREF X 11 11 GND GND 12 12 U3C1_DFP_CC2_HREF X 13 13 U3C1_DFP_CC2 ** NOT TESTED ** 14 14 U3C1_DFP_CC2_O X _____________________________________________________________________________________________________________________________________________________ Totals 2 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 66.7 Testable Pins = 12 UnTested Pins = 4 Analog Coverage = 66.7 Analog Tested Pins = 8 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #10 U3CP1 Loc:C1 Side:T TotalPin:8 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 GND GND 2 2 +5VSB_DUAL VCC 3 3 +5VSB_DUAL VCC 4 4 U3C1_PSW_EN X 5 5 U3C1_PSW_OC_ X 6 6 +5V_U3C_P1 ** NOT TESTED ** 7 7 +5V_U3C_P1 ** NOT TESTED ** 8 8 +5V_U3C_P1 ** NOT TESTED ** _____________________________________________________________________________________________________________________________________________________ Totals 3 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 40.0 Testable Pins = 5 UnTested Pins = 3 Analog Coverage = 40.0 Analog Tested Pins = 2 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #11 U3CP2 Loc:C1 Side:T TotalPin:8 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 GND GND 2 2 +5VSB_DUAL VCC 3 3 +5VSB_DUAL VCC 4 4 U3C1_PSW_EN ** NOT TESTED ** 5 5 U3C1_PSW_OC_ ** NOT TESTED ** 6 6 +5V_U3C_P1 ** NOT TESTED ** 7 7 +5V_U3C_P1 ** NOT TESTED ** 8 8 +5V_U3C_P1 ** NOT TESTED ** _____________________________________________________________________________________________________________________________________________________ Totals 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 0.0 Testable Pins = 5 UnTested Pins = 5 Analog Coverage = 0.0 Analog Tested Pins = 0 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #12 U3U1 Loc:D1 Side:T TotalPin:77 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 +1_2V_U3E1 ** NOT TESTED ** 2 2 U3E1_SMI_ ** NOT TESTED ** 3 3 NC_1797 NC 4 4 +3V VCC 5 5 U3E1_SPI_CLK ** NOT TESTED ** 6 6 U3E1_SPI_SIDO ** NOT TESTED ** 7 7 U3E1_SPI_CS_ ** NOT TESTED ** 8 8 U3E1_SPI_SODI ** NOT TESTED ** 9 9 U3E1_PORST_ ** NOT TESTED ** 10 10 U3E1_UART_RX ** NOT TESTED ** 11 11 U3E1_UART_TX ** NOT TESTED ** 12 12 +1_2V_U3E1 ** NOT TESTED ** 13 13 NC_1798 NC 14 14 NC_1799 NC 15 15 NC_1800 NC 16 16 NC_1801 NC 17 17 NC_1802 NC 18 18 U3E_U2DN2_COL ** NOT TESTED ** 19 19 U3E_U2DP2_COL ** NOT TESTED ** 20 20 +3VSB ** NOT TESTED ** 21 21 +1_2VSB_U3E1 ** NOT TESTED ** 22 22 U3E_U2DN1_COL ** NOT TESTED ** 23 23 U3E_U2DP1_COL ** NOT TESTED ** 24 24 +3VSB ** NOT TESTED ** 25 25 S_WAKE_ ** NOT TESTED ** 26 26 NC_1803 NC 27 27 NC_1804 NC 28 28 U3E_OC_1 ** NOT TESTED ** 29 29 U3E_OC_2 ** NOT TESTED ** 30 30 1142_RST_ ** NOT TESTED ** 31 31 GND GND 32 32 +3V VCC 33 33 +1_2V_U3E1 ** NOT TESTED ** 34 34 +1_2VSB_U3E1 ** NOT TESTED ** 35 35 +1_2VA_U3E1 ** NOT TESTED ** 36 36 U3E_U3RXDP2_COL ** NOT TESTED ** 37 37 U3E_U3RXDN2_COL ** NOT TESTED ** 38 38 +3VA_U3E1 ** NOT TESTED ** 39 39 U3E_U3TXDP2_C ** NOT TESTED ** 40 40 U3E_U3TXDN2_C ** NOT TESTED ** 41 41 +VDD_U3E1 ** NOT TESTED ** 42 42 U3E_U3TXDP1_C ** NOT TESTED ** 43 43 U3E_U3TXDN1_C ** NOT TESTED ** 44 44 +3VA_U3E1 ** NOT TESTED ** 45 45 U3E_U3RXDP1_COL ** NOT TESTED ** 46 46 U3E_U3RXDN1_COL ** NOT TESTED ** 47 47 +1_2VA_U3E1 ** NOT TESTED ** 48 48 CK_100M_U3IC1P ** NOT TESTED ** 49 49 CK_100M_U3IC1N ** NOT TESTED ** 50 50 U3E1_XOUT ** NOT TESTED ** 51 51 U3E1_XIN ** NOT TESTED ** 52 52 +1_2VA_U3E1 ** NOT TESTED ** 53 53 S_X2_U3IC1_TXP0_C ** NOT TESTED ** 54 54 S_X2_U3IC1_TXN0_C ** NOT TESTED ** 55 55 +3VA_U3E1 ** NOT TESTED ** 56 56 S_X2_U3IC1_RXP0_C ** NOT TESTED ** 57 57 S_X2_U3IC1_RXN0_C ** NOT TESTED ** 58 58 +VDD_U3E1 ** NOT TESTED ** 59 59 U3E1_PEREXT ** NOT TESTED ** 60 60 NC_1805 NC 61 61 NC_1806 NC 62 62 +3VA_U3E1 ** NOT TESTED ** 63 63 NC_1807 NC 64 64 NC_1808 NC 65 65 GND GND 66 66 GND GND 67 67 GND GND 68 68 GND GND 69 69 GND GND 70 70 GND GND 71 71 GND GND 72 72 GND GND 73 73 GND GND 74 74 GND GND 75 75 GND GND 76 76 GND GND 77 77 GND GND _____________________________________________________________________________________________________________________________________________________ Totals 16 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 0.0 Testable Pins = 49 UnTested Pins = 49 Analog Coverage = 0.0 Analog Tested Pins = 0 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #13 UAU1 Loc:A1 Side:T TotalPin:48 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 +3V VCC 2 2 A_SPDIFO_HEADER X 3 3 A_REGREF ** NOT TESTED ** 4 4 NC_1949 NC 5 5 S_HD_SDOUT X 6 6 S_HD_BITCLK X 7 7 GND GND 8 8 A_HD_SDIN0_R X 9 9 +DVDD_IO ** NOT TESTED ** 10 10 S_HD_SYNC X 11 11 S_HD_RST_ X 12 12 NC_1950 NC 13 13 A_SENSE_A X 14 14 A_HPOUT_L_C X 15 15 A_HPOUT_R_C X 16 16 A_FMIC1_L_C X 17 17 A_FMIC1_R_C X 18 18 NC_1951 NC 19 19 NC_1952 NC 20 20 NC_1953 NC 21 21 A_MIC1_L_C X 22 22 A_MIC1_R_C X 23 23 A_LINE_L_C X 24 24 A_LINE_R_C X 25 25 +5VA ** NOT TESTED ** 26 26 A_GND GND* 27 27 A_VREF ** NOT TESTED ** 28 28 A_VREF_MIC1_L ** NOT TESTED ** 29 29 +5VA_IN ** NOT TESTED ** 30 30 A_VREF_FMIC1 ** NOT TESTED ** 31 31 A_VREF_FMIC2 ** NOT TESTED ** 32 32 A_VREF_MIC1_R ** NOT TESTED ** 33 33 NC_1954 NC 34 34 A_SENSE_B X 35 35 A_LOUT_L_C X 36 36 A_LOUT_R_C X 37 37 NC_1955 NC 38 38 +5VA ** NOT TESTED ** 39 39 A_SURR_L_C X 40 40 A_JDREF X 41 41 A_SURR_R_C X 42 42 A_GND GND* 43 43 A_CEN_C X 44 44 A_LFE_C X 45 45 A_SIDE_L_C X 46 46 A_SIDE_R_C X 47 47 NC_1956 NC 48 48 NC_1957 NC _____________________________________________________________________________________________________________________________________________________ Totals 4 9 25 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 71.4 Testable Pins = 35 UnTested Pins = 10 Analog Coverage = 71.4 Analog Tested Pins = 25 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #14 UDIA1 Loc:D4 Side:T TotalPin:242 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 H_D3A_VREFDQ ** NOT TESTED ** 2 2 GND GND 3 3 H_D3A_DQ0 ** NOT TESTED ** 4 4 H_D3A_DQ1 ** NOT TESTED ** 5 5 GND GND 6 6 H_D3A_DQSN0 ** NOT TESTED ** 7 7 H_D3A_DQSP0 ** NOT TESTED ** 8 8 GND GND 9 9 H_D3A_DQ2 ** NOT TESTED ** 10 10 H_D3A_DQ3 ** NOT TESTED ** 11 11 GND GND 12 12 H_D3A_DQ8 ** NOT TESTED ** 13 13 H_D3A_DQ9 ** NOT TESTED ** 14 14 GND GND 15 15 H_D3A_DQSN1 ** NOT TESTED ** 16 16 H_D3A_DQSP1 ** NOT TESTED ** 17 17 GND GND 18 18 H_D3A_DQ10 ** NOT TESTED ** 19 19 H_D3A_DQ11 ** NOT TESTED ** 20 20 GND GND 21 21 H_D3A_DQ16 ** NOT TESTED ** 22 22 H_D3A_DQ17 ** NOT TESTED ** 23 23 GND GND 24 24 H_D3A_DQSN2 ** NOT TESTED ** 25 25 H_D3A_DQSP2 ** NOT TESTED ** 26 26 GND GND 27 27 H_D3A_DQ18 ** NOT TESTED ** 28 28 H_D3A_DQ19 ** NOT TESTED ** 29 29 GND GND 30 30 H_D3A_DQ24 ** NOT TESTED ** 31 31 H_D3A_DQ25 ** NOT TESTED ** 32 32 GND GND 33 33 H_D3A_DQSN3 ** NOT TESTED ** 34 34 H_D3A_DQSP3 ** NOT TESTED ** 35 35 GND GND 36 36 H_D3A_DQ26 ** NOT TESTED ** 37 37 H_D3A_DQ27 ** NOT TESTED ** 38 38 GND GND 39 39 NC_1825 ** NOT TESTED ** 40 40 NC_1826 ** NOT TESTED ** 41 41 GND GND 42 42 NC_1827 ** NOT TESTED ** 43 43 NC_1828 ** NOT TESTED ** 44 44 GND GND 45 45 NC_1829 ** NOT TESTED ** 46 46 NC_1830 ** NOT TESTED ** 47 47 GND GND 48 48 NC_1831 ** NOT TESTED ** 49 49 NC_1832 ** NOT TESTED ** 50 50 H_D3A_CKE0 ** NOT TESTED ** 51 51 VDDQ ** NOT TESTED ** 52 52 H_D3A_BA2 ** NOT TESTED ** 53 53 NC_1833 ** NOT TESTED ** 54 54 VDDQ ** NOT TESTED ** 55 55 H_D3A_MA11 ** NOT TESTED ** 56 56 H_D3A_MA7 ** NOT TESTED ** 57 57 VDDQ ** NOT TESTED ** 58 58 H_D3A_MA5 ** NOT TESTED ** 59 59 H_D3A_MA4 ** NOT TESTED ** 60 60 VDDQ ** NOT TESTED ** 61 61 H_D3A_MA2 ** NOT TESTED ** 62 62 VDDQ ** NOT TESTED ** 63 63 H_D3A_CLKP1 ** NOT TESTED ** 64 64 H_D3A_CLKN1 ** NOT TESTED ** 65 65 VDDQ ** NOT TESTED ** 66 66 VDDQ ** NOT TESTED ** 67 67 H_D3A_VREFCA ** NOT TESTED ** 68 68 NC_1834 ** NOT TESTED ** 69 69 VDDQ ** NOT TESTED ** 70 70 H_D3A_MA10 ** NOT TESTED ** 71 71 H_D3A_BA0 ** NOT TESTED ** 72 72 VDDQ ** NOT TESTED ** 73 73 H_D3A_WE_ ** NOT TESTED ** 74 74 H_D3A_CAS_ ** NOT TESTED ** 75 75 VDDQ ** NOT TESTED ** 76 76 H_D3A_CS_1 ** NOT TESTED ** 77 77 H_D3A_ODT1 ** NOT TESTED ** 78 78 VDDQ ** NOT TESTED ** 79 79 NC_1835 ** NOT TESTED ** 80 80 GND GND 81 81 H_D3A_DQ32 ** NOT TESTED ** 82 82 H_D3A_DQ33 ** NOT TESTED ** 83 83 GND GND 84 84 H_D3A_DQSN4 ** NOT TESTED ** 85 85 H_D3A_DQSP4 ** NOT TESTED ** 86 86 GND GND 87 87 H_D3A_DQ34 ** NOT TESTED ** 88 88 H_D3A_DQ35 ** NOT TESTED ** 89 89 GND GND 90 90 H_D3A_DQ40 ** NOT TESTED ** 91 91 H_D3A_DQ41 ** NOT TESTED ** 92 92 GND GND 93 93 H_D3A_DQSN5 ** NOT TESTED ** 94 94 H_D3A_DQSP5 ** NOT TESTED ** 95 95 GND GND 96 96 H_D3A_DQ42 ** NOT TESTED ** 97 97 H_D3A_DQ43 ** NOT TESTED ** 98 98 GND GND 99 99 H_D3A_DQ48 ** NOT TESTED ** 100 100 H_D3A_DQ49 ** NOT TESTED ** 101 101 GND GND 102 102 H_D3A_DQSN6 ** NOT TESTED ** 103 103 H_D3A_DQSP6 ** NOT TESTED ** 104 104 GND GND 105 105 H_D3A_DQ50 ** NOT TESTED ** 106 106 H_D3A_DQ51 ** NOT TESTED ** 107 107 GND GND 108 108 H_D3A_DQ56 ** NOT TESTED ** 109 109 H_D3A_DQ57 ** NOT TESTED ** 110 110 GND GND 111 111 H_D3A_DQSN7 ** NOT TESTED ** 112 112 H_D3A_DQSP7 ** NOT TESTED ** 113 113 GND GND 114 114 H_D3A_DQ58 ** NOT TESTED ** 115 115 H_D3A_DQ59 ** NOT TESTED ** 116 116 GND GND 117 117 GND GND 118 118 S_SMBCLK_MAIN ** NOT TESTED ** 119 119 GND GND 120 120 VTT_DDR ** NOT TESTED ** 121 121 GND GND 122 122 H_D3A_DQ4 ** NOT TESTED ** 123 123 H_D3A_DQ5 ** NOT TESTED ** 124 124 GND GND 125 125 GND GND 126 126 NC_1836 ** NOT TESTED ** 127 127 GND GND 128 128 H_D3A_DQ6 ** NOT TESTED ** 129 129 H_D3A_DQ7 ** NOT TESTED ** 130 130 GND GND 131 131 H_D3A_DQ12 ** NOT TESTED ** 132 132 H_D3A_DQ13 ** NOT TESTED ** 133 133 GND GND 134 134 GND GND 135 135 NC_1837 ** NOT TESTED ** 136 136 GND GND 137 137 H_D3A_DQ14 ** NOT TESTED ** 138 138 H_D3A_DQ15 ** NOT TESTED ** 139 139 GND GND 140 140 H_D3A_DQ20 ** NOT TESTED ** 141 141 H_D3A_DQ21 ** NOT TESTED ** 142 142 GND GND 143 143 GND GND 144 144 NC_1838 ** NOT TESTED ** 145 145 GND GND 146 146 H_D3A_DQ22 ** NOT TESTED ** 147 147 H_D3A_DQ23 ** NOT TESTED ** 148 148 GND GND 149 149 H_D3A_DQ28 ** NOT TESTED ** 150 150 H_D3A_DQ29 ** NOT TESTED ** 151 151 GND GND 152 152 GND GND 153 153 NC_1839 ** NOT TESTED ** 154 154 GND GND 155 155 H_D3A_DQ30 ** NOT TESTED ** 156 156 H_D3A_DQ31 ** NOT TESTED ** 157 157 GND GND 158 158 NC_1840 ** NOT TESTED ** 159 159 NC_1841 ** NOT TESTED ** 160 160 GND GND 161 161 GND GND 162 162 NC_1842 ** NOT TESTED ** 163 163 GND GND 164 164 NC_1843 ** NOT TESTED ** 165 165 NC_1844 ** NOT TESTED ** 166 166 GND GND 167 167 NC_1845 ** NOT TESTED ** 168 168 S_D4_RESET__R ** NOT TESTED ** 169 169 H_D3A_CKE1 ** NOT TESTED ** 170 170 VDDQ ** NOT TESTED ** 171 171 H_D3A_MA15 ** NOT TESTED ** 172 172 H_D3A_MA14 ** NOT TESTED ** 173 173 VDDQ ** NOT TESTED ** 174 174 H_D3A_MA12 ** NOT TESTED ** 175 175 H_D3A_MA9 ** NOT TESTED ** 176 176 VDDQ ** NOT TESTED ** 177 177 H_D3A_MA8 ** NOT TESTED ** 178 178 H_D3A_MA6 ** NOT TESTED ** 179 179 VDDQ ** NOT TESTED ** 180 180 H_D3A_MA3 ** NOT TESTED ** 181 181 H_D3A_MA1 ** NOT TESTED ** 182 182 VDDQ ** NOT TESTED ** 183 183 VDDQ ** NOT TESTED ** 184 184 H_D3A_CLKP0 ** NOT TESTED ** 185 185 H_D3A_CLKN0 ** NOT TESTED ** 186 186 VDDQ ** NOT TESTED ** 187 187 NC_1846 ** NOT TESTED ** 188 188 H_D3A_MA0 ** NOT TESTED ** 189 189 VDDQ ** NOT TESTED ** 190 190 H_D3A_BA1 ** NOT TESTED ** 191 191 VDDQ ** NOT TESTED ** 192 192 H_D3A_RAS_ ** NOT TESTED ** 193 193 H_D3A_CS_0 ** NOT TESTED ** 194 194 VDDQ ** NOT TESTED ** 195 195 H_D3A_ODT0 ** NOT TESTED ** 196 196 H_D3A_MA13 ** NOT TESTED ** 197 197 VDDQ ** NOT TESTED ** 198 198 NC_1847 ** NOT TESTED ** 199 199 GND GND 200 200 H_D3A_DQ36 ** NOT TESTED ** 201 201 H_D3A_DQ37 ** NOT TESTED ** 202 202 GND GND 203 203 GND GND 204 204 NC_1848 ** NOT TESTED ** 205 205 GND GND 206 206 H_D3A_DQ38 ** NOT TESTED ** 207 207 H_D3A_DQ39 ** NOT TESTED ** 208 208 GND GND 209 209 H_D3A_DQ44 ** NOT TESTED ** 210 210 H_D3A_DQ45 ** NOT TESTED ** 211 211 GND GND 212 212 GND GND 213 213 NC_1849 ** NOT TESTED ** 214 214 GND GND 215 215 H_D3A_DQ46 ** NOT TESTED ** 216 216 H_D3A_DQ47 ** NOT TESTED ** 217 217 GND GND 218 218 H_D3A_DQ52 ** NOT TESTED ** 219 219 H_D3A_DQ53 ** NOT TESTED ** 220 220 GND GND 221 221 GND GND 222 222 NC_1850 ** NOT TESTED ** 223 223 GND GND 224 224 H_D3A_DQ54 ** NOT TESTED ** 225 225 H_D3A_DQ55 ** NOT TESTED ** 226 226 GND GND 227 227 H_D3A_DQ60 ** NOT TESTED ** 228 228 H_D3A_DQ61 ** NOT TESTED ** 229 229 GND GND 230 230 GND GND 231 231 NC_1851 ** NOT TESTED ** 232 232 GND GND 233 233 H_D3A_DQ62 ** NOT TESTED ** 234 234 H_D3A_DQ63 ** NOT TESTED ** 235 235 GND GND 236 236 VDDSPD ** NOT TESTED ** 237 237 GND GND 238 238 S_SMBDATA_MAIN ** NOT TESTED ** 239 239 GND GND 240 240 VTT_DDR ** NOT TESTED ** 241 241 NC_1852 NC 242 242 NC_1853 NC _____________________________________________________________________________________________________________________________________________________ Totals 71 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 0.0 Testable Pins = 169 UnTested Pins = 169 Analog Coverage = 0.0 Analog Tested Pins = 0 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #15 UDIA2 Loc:D4 Side:T TotalPin:242 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 H_D3A_VREFDQ ** NOT TESTED ** 2 2 GND GND 3 3 H_D3A_DQ0 ** NOT TESTED ** 4 4 H_D3A_DQ1 ** NOT TESTED ** 5 5 GND GND 6 6 H_D3A_DQSN0 ** NOT TESTED ** 7 7 H_D3A_DQSP0 ** NOT TESTED ** 8 8 GND GND 9 9 H_D3A_DQ2 ** NOT TESTED ** 10 10 H_D3A_DQ3 ** NOT TESTED ** 11 11 GND GND 12 12 H_D3A_DQ8 ** NOT TESTED ** 13 13 H_D3A_DQ9 ** NOT TESTED ** 14 14 GND GND 15 15 H_D3A_DQSN1 ** NOT TESTED ** 16 16 H_D3A_DQSP1 ** NOT TESTED ** 17 17 GND GND 18 18 H_D3A_DQ10 ** NOT TESTED ** 19 19 H_D3A_DQ11 ** NOT TESTED ** 20 20 GND GND 21 21 H_D3A_DQ16 ** NOT TESTED ** 22 22 H_D3A_DQ17 ** NOT TESTED ** 23 23 GND GND 24 24 H_D3A_DQSN2 ** NOT TESTED ** 25 25 H_D3A_DQSP2 ** NOT TESTED ** 26 26 GND GND 27 27 H_D3A_DQ18 ** NOT TESTED ** 28 28 H_D3A_DQ19 ** NOT TESTED ** 29 29 GND GND 30 30 H_D3A_DQ24 ** NOT TESTED ** 31 31 H_D3A_DQ25 ** NOT TESTED ** 32 32 GND GND 33 33 H_D3A_DQSN3 ** NOT TESTED ** 34 34 H_D3A_DQSP3 ** NOT TESTED ** 35 35 GND GND 36 36 H_D3A_DQ26 ** NOT TESTED ** 37 37 H_D3A_DQ27 ** NOT TESTED ** 38 38 GND GND 39 39 NC_1854 ** NOT TESTED ** 40 40 NC_1855 ** NOT TESTED ** 41 41 GND GND 42 42 NC_1856 ** NOT TESTED ** 43 43 NC_1857 ** NOT TESTED ** 44 44 GND GND 45 45 NC_1858 ** NOT TESTED ** 46 46 NC_1859 ** NOT TESTED ** 47 47 GND GND 48 48 NC_1860 ** NOT TESTED ** 49 49 NC_1861 ** NOT TESTED ** 50 50 H_D3A_CKE2 ** NOT TESTED ** 51 51 VDDQ ** NOT TESTED ** 52 52 H_D3A_BA2 ** NOT TESTED ** 53 53 NC_1862 ** NOT TESTED ** 54 54 VDDQ ** NOT TESTED ** 55 55 H_D3A_MA11 ** NOT TESTED ** 56 56 H_D3A_MA7 ** NOT TESTED ** 57 57 VDDQ ** NOT TESTED ** 58 58 H_D3A_MA5 ** NOT TESTED ** 59 59 H_D3A_MA4 ** NOT TESTED ** 60 60 VDDQ ** NOT TESTED ** 61 61 H_D3A_MA2 ** NOT TESTED ** 62 62 VDDQ ** NOT TESTED ** 63 63 H_D3A_CLKP3 ** NOT TESTED ** 64 64 H_D3A_CLKN3 ** NOT TESTED ** 65 65 VDDQ ** NOT TESTED ** 66 66 VDDQ ** NOT TESTED ** 67 67 H_D3A_VREFCA ** NOT TESTED ** 68 68 NC_1863 ** NOT TESTED ** 69 69 VDDQ ** NOT TESTED ** 70 70 H_D3A_MA10 ** NOT TESTED ** 71 71 H_D3A_BA0 ** NOT TESTED ** 72 72 VDDQ ** NOT TESTED ** 73 73 H_D3A_WE_ ** NOT TESTED ** 74 74 H_D3A_CAS_ ** NOT TESTED ** 75 75 VDDQ ** NOT TESTED ** 76 76 H_D3A_CS_3 ** NOT TESTED ** 77 77 H_D3A_ODT3 ** NOT TESTED ** 78 78 VDDQ ** NOT TESTED ** 79 79 NC_1864 ** NOT TESTED ** 80 80 GND GND 81 81 H_D3A_DQ32 ** NOT TESTED ** 82 82 H_D3A_DQ33 ** NOT TESTED ** 83 83 GND GND 84 84 H_D3A_DQSN4 ** NOT TESTED ** 85 85 H_D3A_DQSP4 ** NOT TESTED ** 86 86 GND GND 87 87 H_D3A_DQ34 ** NOT TESTED ** 88 88 H_D3A_DQ35 ** NOT TESTED ** 89 89 GND GND 90 90 H_D3A_DQ40 ** NOT TESTED ** 91 91 H_D3A_DQ41 ** NOT TESTED ** 92 92 GND GND 93 93 H_D3A_DQSN5 ** NOT TESTED ** 94 94 H_D3A_DQSP5 ** NOT TESTED ** 95 95 GND GND 96 96 H_D3A_DQ42 ** NOT TESTED ** 97 97 H_D3A_DQ43 ** NOT TESTED ** 98 98 GND GND 99 99 H_D3A_DQ48 ** NOT TESTED ** 100 100 H_D3A_DQ49 ** NOT TESTED ** 101 101 GND GND 102 102 H_D3A_DQSN6 ** NOT TESTED ** 103 103 H_D3A_DQSP6 ** NOT TESTED ** 104 104 GND GND 105 105 H_D3A_DQ50 ** NOT TESTED ** 106 106 H_D3A_DQ51 ** NOT TESTED ** 107 107 GND GND 108 108 H_D3A_DQ56 ** NOT TESTED ** 109 109 H_D3A_DQ57 ** NOT TESTED ** 110 110 GND GND 111 111 H_D3A_DQSN7 ** NOT TESTED ** 112 112 H_D3A_DQSP7 ** NOT TESTED ** 113 113 GND GND 114 114 H_D3A_DQ58 ** NOT TESTED ** 115 115 H_D3A_DQ59 ** NOT TESTED ** 116 116 GND GND 117 117 VDDSPD ** NOT TESTED ** 118 118 S_SMBCLK_MAIN ** NOT TESTED ** 119 119 GND GND 120 120 VTT_DDR ** NOT TESTED ** 121 121 GND GND 122 122 H_D3A_DQ4 ** NOT TESTED ** 123 123 H_D3A_DQ5 ** NOT TESTED ** 124 124 GND GND 125 125 GND GND 126 126 NC_1865 ** NOT TESTED ** 127 127 GND GND 128 128 H_D3A_DQ6 ** NOT TESTED ** 129 129 H_D3A_DQ7 ** NOT TESTED ** 130 130 GND GND 131 131 H_D3A_DQ12 ** NOT TESTED ** 132 132 H_D3A_DQ13 ** NOT TESTED ** 133 133 GND GND 134 134 GND GND 135 135 NC_1866 ** NOT TESTED ** 136 136 GND GND 137 137 H_D3A_DQ14 ** NOT TESTED ** 138 138 H_D3A_DQ15 ** NOT TESTED ** 139 139 GND GND 140 140 H_D3A_DQ20 ** NOT TESTED ** 141 141 H_D3A_DQ21 ** NOT TESTED ** 142 142 GND GND 143 143 GND GND 144 144 NC_1867 ** NOT TESTED ** 145 145 GND GND 146 146 H_D3A_DQ22 ** NOT TESTED ** 147 147 H_D3A_DQ23 ** NOT TESTED ** 148 148 GND GND 149 149 H_D3A_DQ28 ** NOT TESTED ** 150 150 H_D3A_DQ29 ** NOT TESTED ** 151 151 GND GND 152 152 GND GND 153 153 NC_1868 ** NOT TESTED ** 154 154 GND GND 155 155 H_D3A_DQ30 ** NOT TESTED ** 156 156 H_D3A_DQ31 ** NOT TESTED ** 157 157 GND GND 158 158 NC_1869 ** NOT TESTED ** 159 159 NC_1870 ** NOT TESTED ** 160 160 GND GND 161 161 GND GND 162 162 NC_1871 ** NOT TESTED ** 163 163 GND GND 164 164 NC_1872 ** NOT TESTED ** 165 165 NC_1873 ** NOT TESTED ** 166 166 GND GND 167 167 NC_1874 ** NOT TESTED ** 168 168 S_D4_RESET__R ** NOT TESTED ** 169 169 H_D3A_CKE3 ** NOT TESTED ** 170 170 VDDQ ** NOT TESTED ** 171 171 H_D3A_MA15 ** NOT TESTED ** 172 172 H_D3A_MA14 ** NOT TESTED ** 173 173 VDDQ ** NOT TESTED ** 174 174 H_D3A_MA12 ** NOT TESTED ** 175 175 H_D3A_MA9 ** NOT TESTED ** 176 176 VDDQ ** NOT TESTED ** 177 177 H_D3A_MA8 ** NOT TESTED ** 178 178 H_D3A_MA6 ** NOT TESTED ** 179 179 VDDQ ** NOT TESTED ** 180 180 H_D3A_MA3 ** NOT TESTED ** 181 181 H_D3A_MA1 ** NOT TESTED ** 182 182 VDDQ ** NOT TESTED ** 183 183 VDDQ ** NOT TESTED ** 184 184 H_D3A_CLKP2 ** NOT TESTED ** 185 185 H_D3A_CLKN2 ** NOT TESTED ** 186 186 VDDQ ** NOT TESTED ** 187 187 NC_1875 ** NOT TESTED ** 188 188 H_D3A_MA0 ** NOT TESTED ** 189 189 VDDQ ** NOT TESTED ** 190 190 H_D3A_BA1 ** NOT TESTED ** 191 191 VDDQ ** NOT TESTED ** 192 192 H_D3A_RAS_ ** NOT TESTED ** 193 193 H_D3A_CS_2 ** NOT TESTED ** 194 194 VDDQ ** NOT TESTED ** 195 195 H_D3A_ODT2 ** NOT TESTED ** 196 196 H_D3A_MA13 ** NOT TESTED ** 197 197 VDDQ ** NOT TESTED ** 198 198 NC_1876 ** NOT TESTED ** 199 199 GND GND 200 200 H_D3A_DQ36 ** NOT TESTED ** 201 201 H_D3A_DQ37 ** NOT TESTED ** 202 202 GND GND 203 203 GND GND 204 204 NC_1877 ** NOT TESTED ** 205 205 GND GND 206 206 H_D3A_DQ38 ** NOT TESTED ** 207 207 H_D3A_DQ39 ** NOT TESTED ** 208 208 GND GND 209 209 H_D3A_DQ44 ** NOT TESTED ** 210 210 H_D3A_DQ45 ** NOT TESTED ** 211 211 GND GND 212 212 GND GND 213 213 NC_1878 ** NOT TESTED ** 214 214 GND GND 215 215 H_D3A_DQ46 ** NOT TESTED ** 216 216 H_D3A_DQ47 ** NOT TESTED ** 217 217 GND GND 218 218 H_D3A_DQ52 ** NOT TESTED ** 219 219 H_D3A_DQ53 ** NOT TESTED ** 220 220 GND GND 221 221 GND GND 222 222 NC_1879 ** NOT TESTED ** 223 223 GND GND 224 224 H_D3A_DQ54 ** NOT TESTED ** 225 225 H_D3A_DQ55 ** NOT TESTED ** 226 226 GND GND 227 227 H_D3A_DQ60 ** NOT TESTED ** 228 228 H_D3A_DQ61 ** NOT TESTED ** 229 229 GND GND 230 230 GND GND 231 231 NC_1880 ** NOT TESTED ** 232 232 GND GND 233 233 H_D3A_DQ62 ** NOT TESTED ** 234 234 H_D3A_DQ63 ** NOT TESTED ** 235 235 GND GND 236 236 VDDSPD ** NOT TESTED ** 237 237 GND GND 238 238 S_SMBDATA_MAIN ** NOT TESTED ** 239 239 GND GND 240 240 VTT_DDR ** NOT TESTED ** 241 241 NC_1881 NC 242 242 NC_1882 NC _____________________________________________________________________________________________________________________________________________________ Totals 70 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 0.0 Testable Pins = 170 UnTested Pins = 170 Analog Coverage = 0.0 Analog Tested Pins = 0 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #16 UDIB1 Loc:D4 Side:T TotalPin:242 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 H_D3B_VREFDQ ** NOT TESTED ** 2 2 GND GND 3 3 H_D3B_DQ0 ** NOT TESTED ** 4 4 H_D3B_DQ1 ** NOT TESTED ** 5 5 GND GND 6 6 H_D3B_DQSN0 ** NOT TESTED ** 7 7 H_D3B_DQSP0 ** NOT TESTED ** 8 8 GND GND 9 9 H_D3B_DQ2 ** NOT TESTED ** 10 10 H_D3B_DQ3 ** NOT TESTED ** 11 11 GND GND 12 12 H_D3B_DQ8 ** NOT TESTED ** 13 13 H_D3B_DQ9 ** NOT TESTED ** 14 14 GND GND 15 15 H_D3B_DQSN1 ** NOT TESTED ** 16 16 H_D3B_DQSP1 ** NOT TESTED ** 17 17 GND GND 18 18 H_D3B_DQ10 ** NOT TESTED ** 19 19 H_D3B_DQ11 ** NOT TESTED ** 20 20 GND GND 21 21 H_D3B_DQ16 ** NOT TESTED ** 22 22 H_D3B_DQ17 ** NOT TESTED ** 23 23 GND GND 24 24 H_D3B_DQSN2 ** NOT TESTED ** 25 25 H_D3B_DQSP2 ** NOT TESTED ** 26 26 GND GND 27 27 H_D3B_DQ18 ** NOT TESTED ** 28 28 H_D3B_DQ19 ** NOT TESTED ** 29 29 GND GND 30 30 H_D3B_DQ24 ** NOT TESTED ** 31 31 H_D3B_DQ25 ** NOT TESTED ** 32 32 GND GND 33 33 H_D3B_DQSN3 ** NOT TESTED ** 34 34 H_D3B_DQSP3 ** NOT TESTED ** 35 35 GND GND 36 36 H_D3B_DQ26 ** NOT TESTED ** 37 37 H_D3B_DQ27 ** NOT TESTED ** 38 38 GND GND 39 39 NC_1883 ** NOT TESTED ** 40 40 NC_1884 ** NOT TESTED ** 41 41 GND GND 42 42 NC_1885 ** NOT TESTED ** 43 43 NC_1886 ** NOT TESTED ** 44 44 GND GND 45 45 NC_1887 ** NOT TESTED ** 46 46 NC_1888 ** NOT TESTED ** 47 47 GND GND 48 48 NC_1889 ** NOT TESTED ** 49 49 NC_1890 ** NOT TESTED ** 50 50 H_D3B_CKE0 ** NOT TESTED ** 51 51 VDDQ ** NOT TESTED ** 52 52 H_D3B_BA2 ** NOT TESTED ** 53 53 NC_1891 ** NOT TESTED ** 54 54 VDDQ ** NOT TESTED ** 55 55 H_D3B_MA11 ** NOT TESTED ** 56 56 H_D3B_MA7 ** NOT TESTED ** 57 57 VDDQ ** NOT TESTED ** 58 58 H_D3B_MA5 ** NOT TESTED ** 59 59 H_D3B_MA4 ** NOT TESTED ** 60 60 VDDQ ** NOT TESTED ** 61 61 H_D3B_MA2 ** NOT TESTED ** 62 62 VDDQ ** NOT TESTED ** 63 63 H_D3B_CLKP1 ** NOT TESTED ** 64 64 H_D3B_CLKN1 ** NOT TESTED ** 65 65 VDDQ ** NOT TESTED ** 66 66 VDDQ ** NOT TESTED ** 67 67 H_D3B_VREFCA ** NOT TESTED ** 68 68 NC_1892 ** NOT TESTED ** 69 69 VDDQ ** NOT TESTED ** 70 70 H_D3B_MA10 ** NOT TESTED ** 71 71 H_D3B_BA0 ** NOT TESTED ** 72 72 VDDQ ** NOT TESTED ** 73 73 H_D3B_WE_ ** NOT TESTED ** 74 74 H_D3B_CAS_ ** NOT TESTED ** 75 75 VDDQ ** NOT TESTED ** 76 76 H_D3B_CS_1 ** NOT TESTED ** 77 77 H_D3B_ODT1 ** NOT TESTED ** 78 78 VDDQ ** NOT TESTED ** 79 79 NC_1893 ** NOT TESTED ** 80 80 GND GND 81 81 H_D3B_DQ32 ** NOT TESTED ** 82 82 H_D3B_DQ33 ** NOT TESTED ** 83 83 GND GND 84 84 H_D3B_DQSN4 ** NOT TESTED ** 85 85 H_D3B_DQSP4 ** NOT TESTED ** 86 86 GND GND 87 87 H_D3B_DQ34 ** NOT TESTED ** 88 88 H_D3B_DQ35 ** NOT TESTED ** 89 89 GND GND 90 90 H_D3B_DQ40 ** NOT TESTED ** 91 91 H_D3B_DQ41 ** NOT TESTED ** 92 92 GND GND 93 93 H_D3B_DQSN5 ** NOT TESTED ** 94 94 H_D3B_DQSP5 ** NOT TESTED ** 95 95 GND GND 96 96 H_D3B_DQ42 ** NOT TESTED ** 97 97 H_D3B_DQ43 ** NOT TESTED ** 98 98 GND GND 99 99 H_D3B_DQ48 ** NOT TESTED ** 100 100 H_D3B_DQ49 ** NOT TESTED ** 101 101 GND GND 102 102 H_D3B_DQSN6 ** NOT TESTED ** 103 103 H_D3B_DQSP6 ** NOT TESTED ** 104 104 GND GND 105 105 H_D3B_DQ50 ** NOT TESTED ** 106 106 H_D3B_DQ51 ** NOT TESTED ** 107 107 GND GND 108 108 H_D3B_DQ56 ** NOT TESTED ** 109 109 H_D3B_DQ57 ** NOT TESTED ** 110 110 GND GND 111 111 H_D3B_DQSN7 ** NOT TESTED ** 112 112 H_D3B_DQSP7 ** NOT TESTED ** 113 113 GND GND 114 114 H_D3B_DQ58 ** NOT TESTED ** 115 115 H_D3B_DQ59 ** NOT TESTED ** 116 116 GND GND 117 117 GND GND 118 118 S_SMBCLK_MAIN ** NOT TESTED ** 119 119 GND GND 120 120 VTT_DDR ** NOT TESTED ** 121 121 GND GND 122 122 H_D3B_DQ4 ** NOT TESTED ** 123 123 H_D3B_DQ5 ** NOT TESTED ** 124 124 GND GND 125 125 GND GND 126 126 NC_1894 ** NOT TESTED ** 127 127 GND GND 128 128 H_D3B_DQ6 ** NOT TESTED ** 129 129 H_D3B_DQ7 ** NOT TESTED ** 130 130 GND GND 131 131 H_D3B_DQ12 ** NOT TESTED ** 132 132 H_D3B_DQ13 ** NOT TESTED ** 133 133 GND GND 134 134 GND GND 135 135 NC_1895 ** NOT TESTED ** 136 136 GND GND 137 137 H_D3B_DQ14 ** NOT TESTED ** 138 138 H_D3B_DQ15 ** NOT TESTED ** 139 139 GND GND 140 140 H_D3B_DQ20 ** NOT TESTED ** 141 141 H_D3B_DQ21 ** NOT TESTED ** 142 142 GND GND 143 143 GND GND 144 144 NC_1896 ** NOT TESTED ** 145 145 GND GND 146 146 H_D3B_DQ22 ** NOT TESTED ** 147 147 H_D3B_DQ23 ** NOT TESTED ** 148 148 GND GND 149 149 H_D3B_DQ28 ** NOT TESTED ** 150 150 H_D3B_DQ29 ** NOT TESTED ** 151 151 GND GND 152 152 GND GND 153 153 NC_1897 ** NOT TESTED ** 154 154 GND GND 155 155 H_D3B_DQ30 ** NOT TESTED ** 156 156 H_D3B_DQ31 ** NOT TESTED ** 157 157 GND GND 158 158 NC_1898 ** NOT TESTED ** 159 159 NC_1899 ** NOT TESTED ** 160 160 GND GND 161 161 GND GND 162 162 NC_1900 ** NOT TESTED ** 163 163 GND GND 164 164 NC_1901 ** NOT TESTED ** 165 165 NC_1902 ** NOT TESTED ** 166 166 GND GND 167 167 NC_1903 ** NOT TESTED ** 168 168 S_D4_RESET__R ** NOT TESTED ** 169 169 H_D3B_CKE1 ** NOT TESTED ** 170 170 VDDQ ** NOT TESTED ** 171 171 H_D3B_MA15 ** NOT TESTED ** 172 172 H_D3B_MA14 ** NOT TESTED ** 173 173 VDDQ ** NOT TESTED ** 174 174 H_D3B_MA12 ** NOT TESTED ** 175 175 H_D3B_MA9 ** NOT TESTED ** 176 176 VDDQ ** NOT TESTED ** 177 177 H_D3B_MA8 ** NOT TESTED ** 178 178 H_D3B_MA6 ** NOT TESTED ** 179 179 VDDQ ** NOT TESTED ** 180 180 H_D3B_MA3 ** NOT TESTED ** 181 181 H_D3B_MA1 ** NOT TESTED ** 182 182 VDDQ ** NOT TESTED ** 183 183 VDDQ ** NOT TESTED ** 184 184 H_D3B_CLKP0 ** NOT TESTED ** 185 185 H_D3B_CLKN0 ** NOT TESTED ** 186 186 VDDQ ** NOT TESTED ** 187 187 NC_1904 ** NOT TESTED ** 188 188 H_D3B_MA0 ** NOT TESTED ** 189 189 VDDQ ** NOT TESTED ** 190 190 H_D3B_BA1 ** NOT TESTED ** 191 191 VDDQ ** NOT TESTED ** 192 192 H_D3B_RAS_ ** NOT TESTED ** 193 193 H_D3B_CS_0 ** NOT TESTED ** 194 194 VDDQ ** NOT TESTED ** 195 195 H_D3B_ODT0 ** NOT TESTED ** 196 196 H_D3B_MA13 ** NOT TESTED ** 197 197 VDDQ ** NOT TESTED ** 198 198 NC_1905 ** NOT TESTED ** 199 199 GND GND 200 200 H_D3B_DQ36 ** NOT TESTED ** 201 201 H_D3B_DQ37 ** NOT TESTED ** 202 202 GND GND 203 203 GND GND 204 204 NC_1906 ** NOT TESTED ** 205 205 GND GND 206 206 H_D3B_DQ38 ** NOT TESTED ** 207 207 H_D3B_DQ39 ** NOT TESTED ** 208 208 GND GND 209 209 H_D3B_DQ44 ** NOT TESTED ** 210 210 H_D3B_DQ45 ** NOT TESTED ** 211 211 GND GND 212 212 GND GND 213 213 NC_1907 ** NOT TESTED ** 214 214 GND GND 215 215 H_D3B_DQ46 ** NOT TESTED ** 216 216 H_D3B_DQ47 ** NOT TESTED ** 217 217 GND GND 218 218 H_D3B_DQ52 ** NOT TESTED ** 219 219 H_D3B_DQ53 ** NOT TESTED ** 220 220 GND GND 221 221 GND GND 222 222 NC_1908 ** NOT TESTED ** 223 223 GND GND 224 224 H_D3B_DQ54 ** NOT TESTED ** 225 225 H_D3B_DQ55 ** NOT TESTED ** 226 226 GND GND 227 227 H_D3B_DQ60 ** NOT TESTED ** 228 228 H_D3B_DQ61 ** NOT TESTED ** 229 229 GND GND 230 230 GND GND 231 231 NC_1909 ** NOT TESTED ** 232 232 GND GND 233 233 H_D3B_DQ62 ** NOT TESTED ** 234 234 H_D3B_DQ63 ** NOT TESTED ** 235 235 GND GND 236 236 VDDSPD ** NOT TESTED ** 237 237 VDDSPD ** NOT TESTED ** 238 238 S_SMBDATA_MAIN ** NOT TESTED ** 239 239 GND GND 240 240 VTT_DDR ** NOT TESTED ** 241 241 NC_1910 NC 242 242 NC_1911 NC _____________________________________________________________________________________________________________________________________________________ Totals 70 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 0.0 Testable Pins = 170 UnTested Pins = 170 Analog Coverage = 0.0 Analog Tested Pins = 0 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #17 UDIB2 Loc:D4 Side:T TotalPin:242 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 H_D3B_VREFDQ ** NOT TESTED ** 2 2 GND GND 3 3 H_D3B_DQ0 ** NOT TESTED ** 4 4 H_D3B_DQ1 ** NOT TESTED ** 5 5 GND GND 6 6 H_D3B_DQSN0 ** NOT TESTED ** 7 7 H_D3B_DQSP0 ** NOT TESTED ** 8 8 GND GND 9 9 H_D3B_DQ2 ** NOT TESTED ** 10 10 H_D3B_DQ3 ** NOT TESTED ** 11 11 GND GND 12 12 H_D3B_DQ8 ** NOT TESTED ** 13 13 H_D3B_DQ9 ** NOT TESTED ** 14 14 GND GND 15 15 H_D3B_DQSN1 ** NOT TESTED ** 16 16 H_D3B_DQSP1 ** NOT TESTED ** 17 17 GND GND 18 18 H_D3B_DQ10 ** NOT TESTED ** 19 19 H_D3B_DQ11 ** NOT TESTED ** 20 20 GND GND 21 21 H_D3B_DQ16 ** NOT TESTED ** 22 22 H_D3B_DQ17 ** NOT TESTED ** 23 23 GND GND 24 24 H_D3B_DQSN2 ** NOT TESTED ** 25 25 H_D3B_DQSP2 ** NOT TESTED ** 26 26 GND GND 27 27 H_D3B_DQ18 ** NOT TESTED ** 28 28 H_D3B_DQ19 ** NOT TESTED ** 29 29 GND GND 30 30 H_D3B_DQ24 ** NOT TESTED ** 31 31 H_D3B_DQ25 ** NOT TESTED ** 32 32 GND GND 33 33 H_D3B_DQSN3 ** NOT TESTED ** 34 34 H_D3B_DQSP3 ** NOT TESTED ** 35 35 GND GND 36 36 H_D3B_DQ26 ** NOT TESTED ** 37 37 H_D3B_DQ27 ** NOT TESTED ** 38 38 GND GND 39 39 NC_1912 ** NOT TESTED ** 40 40 NC_1913 ** NOT TESTED ** 41 41 GND GND 42 42 NC_1914 ** NOT TESTED ** 43 43 NC_1915 ** NOT TESTED ** 44 44 GND GND 45 45 NC_1916 ** NOT TESTED ** 46 46 NC_1917 ** NOT TESTED ** 47 47 GND GND 48 48 NC_1918 ** NOT TESTED ** 49 49 NC_1919 ** NOT TESTED ** 50 50 H_D3B_CKE2 ** NOT TESTED ** 51 51 VDDQ ** NOT TESTED ** 52 52 H_D3B_BA2 ** NOT TESTED ** 53 53 NC_1920 ** NOT TESTED ** 54 54 VDDQ ** NOT TESTED ** 55 55 H_D3B_MA11 ** NOT TESTED ** 56 56 H_D3B_MA7 ** NOT TESTED ** 57 57 VDDQ ** NOT TESTED ** 58 58 H_D3B_MA5 ** NOT TESTED ** 59 59 H_D3B_MA4 ** NOT TESTED ** 60 60 VDDQ ** NOT TESTED ** 61 61 H_D3B_MA2 ** NOT TESTED ** 62 62 VDDQ ** NOT TESTED ** 63 63 H_D3B_CLKP3 ** NOT TESTED ** 64 64 H_D3B_CLKN3 ** NOT TESTED ** 65 65 VDDQ ** NOT TESTED ** 66 66 VDDQ ** NOT TESTED ** 67 67 H_D3B_VREFCA ** NOT TESTED ** 68 68 NC_1921 ** NOT TESTED ** 69 69 VDDQ ** NOT TESTED ** 70 70 H_D3B_MA10 ** NOT TESTED ** 71 71 H_D3B_BA0 ** NOT TESTED ** 72 72 VDDQ ** NOT TESTED ** 73 73 H_D3B_WE_ ** NOT TESTED ** 74 74 H_D3B_CAS_ ** NOT TESTED ** 75 75 VDDQ ** NOT TESTED ** 76 76 H_D3B_CS_3 ** NOT TESTED ** 77 77 H_D3B_ODT3 ** NOT TESTED ** 78 78 VDDQ ** NOT TESTED ** 79 79 NC_1922 ** NOT TESTED ** 80 80 GND GND 81 81 H_D3B_DQ32 ** NOT TESTED ** 82 82 H_D3B_DQ33 ** NOT TESTED ** 83 83 GND GND 84 84 H_D3B_DQSN4 ** NOT TESTED ** 85 85 H_D3B_DQSP4 ** NOT TESTED ** 86 86 GND GND 87 87 H_D3B_DQ34 ** NOT TESTED ** 88 88 H_D3B_DQ35 ** NOT TESTED ** 89 89 GND GND 90 90 H_D3B_DQ40 ** NOT TESTED ** 91 91 H_D3B_DQ41 ** NOT TESTED ** 92 92 GND GND 93 93 H_D3B_DQSN5 ** NOT TESTED ** 94 94 H_D3B_DQSP5 ** NOT TESTED ** 95 95 GND GND 96 96 H_D3B_DQ42 ** NOT TESTED ** 97 97 H_D3B_DQ43 ** NOT TESTED ** 98 98 GND GND 99 99 H_D3B_DQ48 ** NOT TESTED ** 100 100 H_D3B_DQ49 ** NOT TESTED ** 101 101 GND GND 102 102 H_D3B_DQSN6 ** NOT TESTED ** 103 103 H_D3B_DQSP6 ** NOT TESTED ** 104 104 GND GND 105 105 H_D3B_DQ50 ** NOT TESTED ** 106 106 H_D3B_DQ51 ** NOT TESTED ** 107 107 GND GND 108 108 H_D3B_DQ56 ** NOT TESTED ** 109 109 H_D3B_DQ57 ** NOT TESTED ** 110 110 GND GND 111 111 H_D3B_DQSN7 ** NOT TESTED ** 112 112 H_D3B_DQSP7 ** NOT TESTED ** 113 113 GND GND 114 114 H_D3B_DQ58 ** NOT TESTED ** 115 115 H_D3B_DQ59 ** NOT TESTED ** 116 116 GND GND 117 117 VDDSPD ** NOT TESTED ** 118 118 S_SMBCLK_MAIN ** NOT TESTED ** 119 119 GND GND 120 120 VTT_DDR ** NOT TESTED ** 121 121 GND GND 122 122 H_D3B_DQ4 ** NOT TESTED ** 123 123 H_D3B_DQ5 ** NOT TESTED ** 124 124 GND GND 125 125 GND GND 126 126 NC_1923 ** NOT TESTED ** 127 127 GND GND 128 128 H_D3B_DQ6 ** NOT TESTED ** 129 129 H_D3B_DQ7 ** NOT TESTED ** 130 130 GND GND 131 131 H_D3B_DQ12 ** NOT TESTED ** 132 132 H_D3B_DQ13 ** NOT TESTED ** 133 133 GND GND 134 134 GND GND 135 135 NC_1924 ** NOT TESTED ** 136 136 GND GND 137 137 H_D3B_DQ14 ** NOT TESTED ** 138 138 H_D3B_DQ15 ** NOT TESTED ** 139 139 GND GND 140 140 H_D3B_DQ20 ** NOT TESTED ** 141 141 H_D3B_DQ21 ** NOT TESTED ** 142 142 GND GND 143 143 GND GND 144 144 NC_1925 ** NOT TESTED ** 145 145 GND GND 146 146 H_D3B_DQ22 ** NOT TESTED ** 147 147 H_D3B_DQ23 ** NOT TESTED ** 148 148 GND GND 149 149 H_D3B_DQ28 ** NOT TESTED ** 150 150 H_D3B_DQ29 ** NOT TESTED ** 151 151 GND GND 152 152 GND GND 153 153 NC_1926 ** NOT TESTED ** 154 154 GND GND 155 155 H_D3B_DQ30 ** NOT TESTED ** 156 156 H_D3B_DQ31 ** NOT TESTED ** 157 157 GND GND 158 158 NC_1927 ** NOT TESTED ** 159 159 NC_1928 ** NOT TESTED ** 160 160 GND GND 161 161 GND GND 162 162 NC_1929 ** NOT TESTED ** 163 163 GND GND 164 164 NC_1930 ** NOT TESTED ** 165 165 NC_1931 ** NOT TESTED ** 166 166 GND GND 167 167 NC_1932 ** NOT TESTED ** 168 168 S_D4_RESET__R ** NOT TESTED ** 169 169 H_D3B_CKE3 ** NOT TESTED ** 170 170 VDDQ ** NOT TESTED ** 171 171 H_D3B_MA15 ** NOT TESTED ** 172 172 H_D3B_MA14 ** NOT TESTED ** 173 173 VDDQ ** NOT TESTED ** 174 174 H_D3B_MA12 ** NOT TESTED ** 175 175 H_D3B_MA9 ** NOT TESTED ** 176 176 VDDQ ** NOT TESTED ** 177 177 H_D3B_MA8 ** NOT TESTED ** 178 178 H_D3B_MA6 ** NOT TESTED ** 179 179 VDDQ ** NOT TESTED ** 180 180 H_D3B_MA3 ** NOT TESTED ** 181 181 H_D3B_MA1 ** NOT TESTED ** 182 182 VDDQ ** NOT TESTED ** 183 183 VDDQ ** NOT TESTED ** 184 184 H_D3B_CLKP2 ** NOT TESTED ** 185 185 H_D3B_CLKN2 ** NOT TESTED ** 186 186 VDDQ ** NOT TESTED ** 187 187 NC_1933 ** NOT TESTED ** 188 188 H_D3B_MA0 ** NOT TESTED ** 189 189 VDDQ ** NOT TESTED ** 190 190 H_D3B_BA1 ** NOT TESTED ** 191 191 VDDQ ** NOT TESTED ** 192 192 H_D3B_RAS_ ** NOT TESTED ** 193 193 H_D3B_CS_2 ** NOT TESTED ** 194 194 VDDQ ** NOT TESTED ** 195 195 H_D3B_ODT2 ** NOT TESTED ** 196 196 H_D3B_MA13 ** NOT TESTED ** 197 197 VDDQ ** NOT TESTED ** 198 198 NC_1934 ** NOT TESTED ** 199 199 GND GND 200 200 H_D3B_DQ36 ** NOT TESTED ** 201 201 H_D3B_DQ37 ** NOT TESTED ** 202 202 GND GND 203 203 GND GND 204 204 NC_1935 ** NOT TESTED ** 205 205 GND GND 206 206 H_D3B_DQ38 ** NOT TESTED ** 207 207 H_D3B_DQ39 ** NOT TESTED ** 208 208 GND GND 209 209 H_D3B_DQ44 ** NOT TESTED ** 210 210 H_D3B_DQ45 ** NOT TESTED ** 211 211 GND GND 212 212 GND GND 213 213 NC_1936 ** NOT TESTED ** 214 214 GND GND 215 215 H_D3B_DQ46 ** NOT TESTED ** 216 216 H_D3B_DQ47 ** NOT TESTED ** 217 217 GND GND 218 218 H_D3B_DQ52 ** NOT TESTED ** 219 219 H_D3B_DQ53 ** NOT TESTED ** 220 220 GND GND 221 221 GND GND 222 222 NC_1937 ** NOT TESTED ** 223 223 GND GND 224 224 H_D3B_DQ54 ** NOT TESTED ** 225 225 H_D3B_DQ55 ** NOT TESTED ** 226 226 GND GND 227 227 H_D3B_DQ60 ** NOT TESTED ** 228 228 H_D3B_DQ61 ** NOT TESTED ** 229 229 GND GND 230 230 GND GND 231 231 NC_1938 ** NOT TESTED ** 232 232 GND GND 233 233 H_D3B_DQ62 ** NOT TESTED ** 234 234 H_D3B_DQ63 ** NOT TESTED ** 235 235 GND GND 236 236 VDDSPD ** NOT TESTED ** 237 237 VDDSPD ** NOT TESTED ** 238 238 S_SMBDATA_MAIN ** NOT TESTED ** 239 239 GND GND 240 240 VTT_DDR ** NOT TESTED ** 241 241 NC_1939 NC 242 242 NC_1940 NC _____________________________________________________________________________________________________________________________________________________ Totals 69 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 0.0 Testable Pins = 171 UnTested Pins = 171 Analog Coverage = 0.0 Analog Tested Pins = 0 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #18 UGU1 Loc:E1 Side:T TotalPin:38 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 VGA_VSYNC X 2 2 VGA_HSYNC X 3 3 N09933 ** NOT TESTED ** 4 4 +1_8V_VDDC ** NOT TESTED ** 5 5 VGA_BLUE ** NOT TESTED ** 6 6 VGA_GREEN ** NOT TESTED ** 7 7 VGA_RED ** NOT TESTED ** 8 8 +3V_DP2VGA VCC 9 9 +1_8V_IVDDO ** NOT TESTED ** 10 10 VGA_DDC_CLK ** NOT TESTED ** 11 11 VGA_DDC_DATA ** NOT TESTED ** 12 12 VGA_DDC_DATA ** NOT TESTED ** 13 13 VGA_DDC_CLK ** NOT TESTED ** 14 14 H_DP2VGA_AUXN_C ** NOT TESTED ** 15 15 H_DP2VGA_AUXP_C ** NOT TESTED ** 16 16 +1_8V_IVDDO ** NOT TESTED ** 17 17 +1_8V_AVCC ** NOT TESTED ** 18 18 H_DP2VGA_TXP0_C ** NOT TESTED ** 19 19 H_DP2VGA_TXN0_C ** NOT TESTED ** 20 20 H_DP2VGA_TXP1_C ** NOT TESTED ** 21 21 H_DP2VGA_TXN1_C ** NOT TESTED ** 22 22 +1_8V_AVCC ** NOT TESTED ** 23 23 +3V_DP2VGA VCC 24 24 EDID_SELECT X 25 25 +1_8V_IVDDO ** NOT TESTED ** 26 26 S_DP2VGA_HPD ** NOT TESTED ** 27 27 NC_1820 NC 28 28 NC_1821 NC 29 29 NC_1822 NC 30 30 +1_8V_IVDDO ** NOT TESTED ** 31 31 +1_8V_IVDDO ** NOT TESTED ** 32 32 +3V_DP2VGA VCC 33 33 GND GND 34 34 GND GND 35 35 GND GND 36 36 GND GND 37 37 GND GND 38 38 GND GND _____________________________________________________________________________________________________________________________________________________ Totals 9 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 11.5 Testable Pins = 26 UnTested Pins = 23 Analog Coverage = 11.5 Analog Tested Pins = 3 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #19 UGU2 Loc:E1 Side:T TotalPin:53 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 SQ_EN2 GND* 2 2 +3V_DVI VCC 3 3 CG_0 X 4 4 CG_1 X 5 5 GND GND 6 6 REXT X 7 7 S_HDMI_HPD ** NOT TESTED ** 8 8 S_HDMI_DDC_DATA ** NOT TESTED ** 9 9 S_HDMI_DDC_CLK ** NOT TESTED ** 10 10 CG_2 X 11 11 +3V_DVI VCC 12 12 GND GND 13 13 SW_HDMI_TXCN_R ** NOT TESTED ** 14 14 SW_HDMI_TXCP_R ** NOT TESTED ** 15 15 +3V_DVI VCC 16 16 SW_HDMI_TXDN0_R ** NOT TESTED ** 17 17 SW_HDMI_TXDP0_R ** NOT TESTED ** 18 18 GND GND 19 19 SW_HDMI_TXDN1_R ** NOT TESTED ** 20 20 SW_HDMI_TXDP1_R ** NOT TESTED ** 21 21 +3V_DVI VCC 22 22 SW_HDMI_TXDN2_R ** NOT TESTED ** 23 23 SW_HDMI_TXDP2_R ** NOT TESTED ** 24 24 GND GND 25 25 S_LS_OE__HDMI X 26 26 +3V_DVI VCC 27 27 GND GND 28 28 SW_HDMI_DDC_CLK X 29 29 SW_HDMI_DDC_DATA X 30 30 SW_HDMI_HPD X 31 31 GND GND 32 32 G_LS_DDC_EN_HDMI X 33 33 +3V_DVI VCC 34 34 EQ_0 X 35 35 EQ_1 X 36 36 DC_EN2 GND* 37 37 GND GND 38 38 H_HDMI_TXDP2_C ** NOT TESTED ** 39 39 H_HDMI_TXDN2_C ** NOT TESTED ** 40 40 +3V_DVI VCC 41 41 H_HDMI_TXDP1_C ** NOT TESTED ** 42 42 H_HDMI_TXDN1_C ** NOT TESTED ** 43 43 GND GND 44 44 H_HDMI_TXDP0_C ** NOT TESTED ** 45 45 H_HDMI_TXDN0_C ** NOT TESTED ** 46 46 +3V_DVI VCC 47 47 H_HDMI_TXCP_C ** NOT TESTED ** 48 48 H_HDMI_TXCN_C ** NOT TESTED ** 49 49 GND GND 50 50 GND GND 51 51 GND GND 52 52 GND GND 53 53 GND GND _____________________________________________________________________________________________________________________________________________________ Totals 23 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 36.7 Testable Pins = 30 UnTested Pins = 19 Analog Coverage = 36.7 Analog Tested Pins = 11 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #20 UK1U1 Loc:B2 Side:T TotalPin:128 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 K_SERR_ X 2 2 GND GND 3 3 +3V ** NOT TESTED ** 4 4 K_PERR_ X 5 5 K_LOCK_ X 6 6 K_STOP_ X 7 7 GND GND 8 8 +1_2V_EPCI ** NOT TESTED ** 9 9 K_DEVSEL_ X 10 10 K_TRDY_ X 11 11 K_IRDY_ X 12 12 K_FRAME_ X 13 13 GND GND 14 14 +3V ** NOT TESTED ** 15 15 K_C_BE_2 X 16 16 K_AD16 X 17 17 K_AD17 X 18 18 K_AD18 X 19 19 K_AD19 X 20 20 K_AD20 X 21 21 K_AD21 X 22 22 GND GND 23 23 +3V ** NOT TESTED ** 24 24 K_AD22 X 25 25 K_AD23 X 26 26 K_C_BE_3 X 27 27 K_AD24 X 28 28 K_AD25 X 29 29 K_AD26 X 30 30 K_AD27 X 31 31 GND GND 32 32 +3V ** NOT TESTED ** 33 33 K_AD28 X 34 34 K_AD29 X 35 35 K_AD30 X 36 36 K_AD31 X 37 37 K_PME_ X 38 38 K_PCIRST_ X 39 39 K_REQ_4 X 40 40 NC_1984 NC 41 41 GND GND 42 42 +3V ** NOT TESTED ** 43 43 K_REQ_3 X 44 44 NC_1985 NC 45 45 K_REQ_2 X 46 46 GND GND 47 47 +1_2V_EPCI ** NOT TESTED ** 48 48 NC_1986 NC 49 49 K_REQ_1 X 50 50 NC_1987 NC 51 51 K_REQ_0 X 52 52 GND GND 53 53 +3V ** NOT TESTED ** 54 54 K_GNT_0 X 55 55 K_INTD_ X 56 56 K_INTC_ X 57 57 K_INTB_ X 58 58 K_INTA_ X 59 59 NC_1988 NC 60 60 K1_CLKRUN_EN_ X 61 61 CK_33M_SL1_R X 62 62 NC_1989 NC 63 63 GND GND 64 64 +3V ** NOT TESTED ** 65 65 NC_1990 NC 66 66 NC_1991 NC 67 67 NC_1992 NC 68 68 NC_1993 NC 69 69 NC_1994 NC 70 70 NC_1995 NC 71 71 GND GND 72 72 NC_1996 NC 73 73 K1_CLK100SEL X 74 74 GND GND 75 75 GND GND 76 76 NC_1997 NC 77 77 +1_2V_EPCI ** NOT TESTED ** 78 78 CK_100M_EPCIP ** NOT TESTED ** 79 79 CK_100M_EPCIN ** NOT TESTED ** 80 80 GND GND 81 81 +1_2VA_EPCI ** NOT TESTED ** 82 82 GND GND 83 83 S_X1_EPCI_TXP_C ** NOT TESTED ** 84 84 S_X1_EPCI_TXN_C ** NOT TESTED ** 85 85 GND GND 86 86 S_X1_EPCI_RXP_C ** NOT TESTED ** 87 87 S_X1_EPCI_RXN_C ** NOT TESTED ** 88 88 GND GND 89 89 +1_2VA_EPCI ** NOT TESTED ** 90 90 +3VA_EPCI ** NOT TESTED ** 91 91 K1_PEREXT X 92 92 NC_1998 NC 93 93 NC_1999 NC 94 94 NC_2000 NC 95 95 K1_PWRDET_ ** NOT TESTED ** 96 96 S_PLTRST_ ** NOT TESTED ** 97 97 GND GND 98 98 +3V ** NOT TESTED ** 99 99 GND GND 100 100 GND GND 101 101 GND GND 102 102 GND GND 103 103 +1_2V_EPCI ** NOT TESTED ** 104 104 GND GND 105 105 K_AD0 X 106 106 K_AD1 X 107 107 K_AD2 X 108 108 K_AD3 X 109 109 K_AD4 X 110 110 GND GND 111 111 +3V ** NOT TESTED ** 112 112 K_AD5 X 113 113 K_AD6 X 114 114 K_AD7 X 115 115 K_AD8 X 116 116 K_C_BE_0 X 117 117 GND GND 118 118 K_AD9 X 119 119 K_AD10 X 120 120 K_AD11 X 121 121 GND GND 122 122 +3V ** NOT TESTED ** 123 123 K_AD12 X 124 124 K_AD13 X 125 125 K_AD14 X 126 126 K_AD15 X 127 127 K_C_BE_1 X 128 128 K_PAR X _____________________________________________________________________________________________________________________________________________________ Totals 25 17 61 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 70.9 Testable Pins = 86 UnTested Pins = 25 Analog Coverage = 70.9 Analog Tested Pins = 61 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #21 ULGA1 Loc:D3 Side:T TotalPin:1151 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 GND GND 2 2 H_X16_SL1_TXP0 ** NOT TESTED ** 3 3 H_X16_SL1_TXN0 ** NOT TESTED ** 4 4 GND GND 5 5 GND GND 6 6 N23361772 ** NOT TESTED ** 7 7 GND GND 8 8 NC_2137 NC 9 9 GND GND 10 10 NC_2138 NC 11 11 GND GND 12 12 H_HDMI_TXDN2 ** NOT TESTED ** 13 13 H_DVI_TXDN0 ** NOT TESTED ** 14 14 GND GND 15 15 VCORE ** NOT TESTED ** 16 16 VCORE ** NOT TESTED ** 17 17 VCORE ** NOT TESTED ** 18 18 VCORE ** NOT TESTED ** 19 19 VCORE ** NOT TESTED ** 20 20 VCORE ** NOT TESTED ** 21 21 H_CPU_TRIGGER_R ** NOT TESTED ** 22 22 H_X16_SL1_TXP1 ** NOT TESTED ** 23 23 H_X16_SL1_TXN1 ** NOT TESTED ** 24 24 GND GND 25 25 H_X16_SL1_RXN0 ** NOT TESTED ** 26 26 H_X16_SL1_RXP0 ** NOT TESTED ** 27 27 H_PREQ_ ** NOT TESTED ** 28 28 H_PRDY_ ** NOT TESTED ** 29 29 NC_2165 NC 30 30 N23361774 ** NOT TESTED ** 31 31 N23361804 ** NOT TESTED ** 32 32 NC_2166 NC 33 33 NC_2167 NC 34 34 NC_2168 NC 35 35 NC_2169 NC 36 36 H_HDMI_TXDP2 ** NOT TESTED ** 37 37 H_DVI_TXDP0 ** NOT TESTED ** 38 38 GND GND 39 39 VCORE ** NOT TESTED ** 40 40 GND GND 41 41 VCORE ** NOT TESTED ** 42 42 GND GND 43 43 VCORE ** NOT TESTED ** 44 44 GND GND 45 45 VCORE ** NOT TESTED ** 46 46 VCORE ** NOT TESTED ** 47 47 VCORE ** NOT TESTED ** 48 48 VCORE ** NOT TESTED ** 49 49 VCORE ** NOT TESTED ** 50 50 VCORE ** NOT TESTED ** 51 51 VCORE ** NOT TESTED ** 52 52 P_CPU_GND_VCORE ** NOT TESTED ** 53 53 N95739044 ** NOT TESTED ** 54 54 GND GND 55 55 H_X16_SL1_TXP2 ** NOT TESTED ** 56 56 H_X16_SL1_TXN2 ** NOT TESTED ** 57 57 GND GND 58 58 H_X16_SL1_RXN1 ** NOT TESTED ** 59 59 H_X16_SL1_RXP1 ** NOT TESTED ** 60 60 GND GND 61 61 N97270486 ** NOT TESTED ** 62 62 GND GND 63 63 NC_2170 NC 64 64 GND GND 65 65 N23361806 ** NOT TESTED ** 66 66 GND GND 67 67 NC_2171 NC 68 68 GND GND 69 69 NC_2172 NC 70 70 GND GND 71 71 H_HDMI_TXDP0 ** NOT TESTED ** 72 72 GND GND 73 73 H_DVI_TXDP2 ** NOT TESTED ** 74 74 GND GND 75 75 H_DVI_TXCP ** NOT TESTED ** 76 76 GND GND 77 77 VCORE ** NOT TESTED ** 78 78 VCORE ** NOT TESTED ** 79 79 VCORE ** NOT TESTED ** 80 80 VCORE ** NOT TESTED ** 81 81 VCORE ** NOT TESTED ** 82 82 VCORE ** NOT TESTED ** 83 83 GND GND 84 84 VCORE ** NOT TESTED ** 85 85 GND GND 86 86 VCORE ** NOT TESTED ** 87 87 GND GND 88 88 VCORE ** NOT TESTED ** 89 89 GND GND 90 90 H_VCC_SENSE ** NOT TESTED ** 91 91 H_PROCHOT__R ** NOT TESTED ** 92 92 N95739050 ** NOT TESTED ** 93 93 S_CPU_TRIGGER ** NOT TESTED ** 94 94 H_X16_SL1_TXP3 ** NOT TESTED ** 95 95 H_X16_SL1_TXN3 ** NOT TESTED ** 96 96 GND GND 97 97 H_X16_SL1_RXN2 ** NOT TESTED ** 98 98 H_X16_SL1_RXP2 ** NOT TESTED ** 99 99 GND GND 100 100 H_PM_DOWN_R ** NOT TESTED ** 101 101 N97270483 ** NOT TESTED ** 102 102 N97270480 ** NOT TESTED ** 103 103 H_THERMTRIP_ ** NOT TESTED ** 104 104 H_DP2VGA_AUXP ** NOT TESTED ** 105 105 H_CATERR_ ** NOT TESTED ** 106 106 H_EDP_DISP_UTIL ** NOT TESTED ** 107 107 N95739470 ** NOT TESTED ** 108 108 SKL_XDP_MBP_0 ** NOT TESTED ** 109 109 SKL_XDP_MBP_1 ** NOT TESTED ** 110 110 H_HDMI_TXDP1 ** NOT TESTED ** 111 111 H_HDMI_TXDN0 ** NOT TESTED ** 112 112 H_HDMI_TXCP ** NOT TESTED ** 113 113 H_DVI_TXDN2 ** NOT TESTED ** 114 114 H_DVI_TXDP1 ** NOT TESTED ** 115 115 H_DVI_TXCN ** NOT TESTED ** 116 116 GND GND 117 117 VCORE ** NOT TESTED ** 118 118 GND GND 119 119 VCORE ** NOT TESTED ** 120 120 GND GND 121 121 VCORE ** NOT TESTED ** 122 122 GND GND 123 123 VCORE ** NOT TESTED ** 124 124 VCORE ** NOT TESTED ** 125 125 VCORE ** NOT TESTED ** 126 126 VCORE ** NOT TESTED ** 127 127 VCORE ** NOT TESTED ** 128 128 VCORE ** NOT TESTED ** 129 129 GND GND 130 130 H_VSS_SENSE ** NOT TESTED ** 131 131 GND GND 132 132 GND GND 133 133 H_X16_SL1_TXP4 ** NOT TESTED ** 134 134 H_X16_SL1_TXN4 ** NOT TESTED ** 135 135 GND GND 136 136 H_X16_SL1_RXN3 ** NOT TESTED ** 137 137 H_X16_SL1_RXP3 ** NOT TESTED ** 138 138 GND GND 139 139 H_CPURST_ ** NOT TESTED ** 140 140 S_PM_SYNC ** NOT TESTED ** 141 141 GND GND 142 142 N97270477 ** NOT TESTED ** 143 143 GND GND 144 144 H_DP2VGA_AUXN ** NOT TESTED ** 145 145 GND GND 146 146 H_CFG16 ** NOT TESTED ** 147 147 GND GND 148 148 H_CFG9 ** NOT TESTED ** 149 149 GND GND 150 150 H_HDMI_TXDN1 ** NOT TESTED ** 151 151 GND GND 152 152 H_HDMI_TXCN ** NOT TESTED ** 153 153 GND GND 154 154 H_DVI_TXDN1 ** NOT TESTED ** 155 155 GND GND 156 156 VCORE ** NOT TESTED ** 157 157 VCORE ** NOT TESTED ** 158 158 VCORE ** NOT TESTED ** 159 159 VCORE ** NOT TESTED ** 160 160 VCORE ** NOT TESTED ** 161 161 VCORE ** NOT TESTED ** 162 162 VCORE ** NOT TESTED ** 163 163 GND GND 164 164 VCORE ** NOT TESTED ** 165 165 GND GND 166 166 VCORE ** NOT TESTED ** 167 167 GND GND 168 168 VCORE ** NOT TESTED ** 169 169 GND GND 170 170 H_SVID_CLK ** NOT TESTED ** 171 171 H_SVID_ALERT__R ** NOT TESTED ** 172 172 H_SVID_DATA ** NOT TESTED ** 173 173 GND GND 174 174 H_X16_SL1_TXP5 ** NOT TESTED ** 175 175 H_X16_SL1_TXN5 ** NOT TESTED ** 176 176 GND GND 177 177 H_X16_SL1_RXN4 ** NOT TESTED ** 178 178 H_X16_SL1_RXP4 ** NOT TESTED ** 179 179 GND GND 180 180 H_CPUPWRGD ** NOT TESTED ** 181 181 H_DP2VGA_TXP1 ** NOT TESTED ** 182 182 GND GND 183 183 H_TCK ** NOT TESTED ** 184 184 H_TRST_ ** NOT TESTED ** 185 185 H_TMS ** NOT TESTED ** 186 186 H_CFG17 ** NOT TESTED ** 187 187 H_CFG1 ** NOT TESTED ** 188 188 H_CFG2 ** NOT TESTED ** 189 189 H_CFG10 ** NOT TESTED ** 190 190 H_CFG19 ** NOT TESTED ** 191 191 H_CFG4 ** NOT TESTED ** 192 192 H_CFG13 ** NOT TESTED ** 193 193 H_CFG14 ** NOT TESTED ** 194 194 GND GND 195 195 VCORE ** NOT TESTED ** 196 196 VCORE ** NOT TESTED ** 197 197 VCORE ** NOT TESTED ** 198 198 GND GND 199 199 VCORE ** NOT TESTED ** 200 200 GND GND 201 201 VCORE ** NOT TESTED ** 202 202 GND GND 203 203 VCORE ** NOT TESTED ** 204 204 VCORE ** NOT TESTED ** 205 205 VCORE ** NOT TESTED ** 206 206 VCORE ** NOT TESTED ** 207 207 N95876428 ** NOT TESTED ** 208 208 N96092497 ** NOT TESTED ** 209 209 N96092506 ** NOT TESTED ** 210 210 H_GT_VSS_SENSE ** NOT TESTED ** 211 211 H_GT_VCC_SENSE ** NOT TESTED ** 212 212 GND GND 213 213 H_X16_SL1_TXP6 ** NOT TESTED ** 214 214 H_X16_SL1_TXN6 ** NOT TESTED ** 215 215 GND GND 216 216 H_X16_SL1_RXN5 ** NOT TESTED ** 217 217 H_X16_SL1_RXP5 ** NOT TESTED ** 218 218 GND GND 219 219 O_H_PECI ** NOT TESTED ** 220 220 GND GND 221 221 H_DP2VGA_TXN1 ** NOT TESTED ** 222 222 H_DP2VGA_TXP0 ** NOT TESTED ** 223 223 GND GND 224 224 H_TDI ** NOT TESTED ** 225 225 GND GND 226 226 H_MBP_2 ** NOT TESTED ** 227 227 GND GND 228 228 H_CFG8 ** NOT TESTED ** 229 229 GND GND 230 230 H_CFG18 ** NOT TESTED ** 231 231 GND GND 232 232 H_CFG12 ** NOT TESTED ** 233 233 H_CFG6 ** NOT TESTED ** 234 234 GND GND 235 235 VCORE ** NOT TESTED ** 236 236 VCORE ** NOT TESTED ** 237 237 VCORE ** NOT TESTED ** 238 238 VCORE ** NOT TESTED ** 239 239 VCORE ** NOT TESTED ** 240 240 VCORE ** NOT TESTED ** 241 241 VCORE ** NOT TESTED ** 242 242 VCORE ** NOT TESTED ** 243 243 GND GND 244 244 VCORE ** NOT TESTED ** 245 245 GND GND 246 246 N95876428 ** NOT TESTED ** 247 247 N95876428 ** NOT TESTED ** 248 248 VCCGT ** NOT TESTED ** 249 249 VCCGT ** NOT TESTED ** 250 250 VCCGT ** NOT TESTED ** 251 251 VCCGT ** NOT TESTED ** 252 252 VCCGT ** NOT TESTED ** 253 253 GND GND 254 254 H_X16_SL1_TXP7 ** NOT TESTED ** 255 255 H_X16_SL1_TXN7 ** NOT TESTED ** 256 256 GND GND 257 257 H_X16_SL1_RXN6 ** NOT TESTED ** 258 258 H_X16_SL1_RXP6 ** NOT TESTED ** 259 259 GND GND 260 260 GND GND 261 261 GND GND 262 262 H_DP2VGA_TXN0 ** NOT TESTED ** 263 263 N95739195 ** NOT TESTED ** 264 264 N95739198 ** NOT TESTED ** 265 265 H_TDO ** NOT TESTED ** 266 266 H_MBP_3 ** NOT TESTED ** 267 267 H_CFG0 ** NOT TESTED ** 268 268 H_CFG3 ** NOT TESTED ** 269 269 H_CFG11 ** NOT TESTED ** 270 270 H_CFG5_R ** NOT TESTED ** 271 271 H_CFG15 ** NOT TESTED ** 272 272 H_CFG7 ** NOT TESTED ** 273 273 GND GND 274 274 VCORE ** NOT TESTED ** 275 275 VCORE ** NOT TESTED ** 276 276 GND GND 277 277 VCORE ** NOT TESTED ** 278 278 GND GND 279 279 VCORE ** NOT TESTED ** 280 280 GND GND 281 281 VCORE ** NOT TESTED ** 282 282 GND GND 283 283 VCORE ** NOT TESTED ** 284 284 VCORE ** NOT TESTED ** 285 285 N95876428 ** NOT TESTED ** 286 286 N95876428 ** NOT TESTED ** 287 287 GND GND 288 288 VCCGT ** NOT TESTED ** 289 289 GND GND 290 290 VCCGT ** NOT TESTED ** 291 291 GND GND 292 292 VCCGT ** NOT TESTED ** 293 293 H_X16_SL1_TXP8 ** NOT TESTED ** 294 294 H_X16_SL1_TXN8 ** NOT TESTED ** 295 295 GND GND 296 296 H_X16_SL1_RXN7 ** NOT TESTED ** 297 297 H_X16_SL1_RXP7 ** NOT TESTED ** 298 298 GND GND 299 299 N95738970 ** NOT TESTED ** 300 300 N95738918 ** NOT TESTED ** 301 301 CK_24M_NSCCCLKN ** NOT TESTED ** 302 302 GND GND 303 303 N95739444 ** NOT TESTED ** 304 304 GND GND 305 305 N95739273 ** NOT TESTED ** 306 306 N95739244 ** NOT TESTED ** 307 307 N95739241 ** NOT TESTED ** 308 308 GND GND 309 309 N95739041 ** NOT TESTED ** 310 310 GND GND 311 311 N95739047 ** NOT TESTED ** 312 312 GND GND 313 313 VCORE ** NOT TESTED ** 314 314 VCORE ** NOT TESTED ** 315 315 VCORE ** NOT TESTED ** 316 316 VCORE ** NOT TESTED ** 317 317 VCORE ** NOT TESTED ** 318 318 VCORE ** NOT TESTED ** 319 319 VCORE ** NOT TESTED ** 320 320 VCORE ** NOT TESTED ** 321 321 VCORE ** NOT TESTED ** 322 322 VCORE ** NOT TESTED ** 323 323 VCORE ** NOT TESTED ** 324 324 GND GND 325 325 N95876428 ** NOT TESTED ** 326 326 GND GND 327 327 N95876428 ** NOT TESTED ** 328 328 VCCGT ** NOT TESTED ** 329 329 VCCGT ** NOT TESTED ** 330 330 VCCGT ** NOT TESTED ** 331 331 VCCGT ** NOT TESTED ** 332 332 VCCGT ** NOT TESTED ** 333 333 GND GND 334 334 H_X16_SL1_TXP9 ** NOT TESTED ** 335 335 H_X16_SL1_TXN9 ** NOT TESTED ** 336 336 GND GND 337 337 H_X16_SL1_RXN8 ** NOT TESTED ** 338 338 H_X16_SL1_RXP8 ** NOT TESTED ** 339 339 GND GND 340 340 N95738976 ** NOT TESTED ** 341 341 CK_24M_NSCCCLKP ** NOT TESTED ** 342 342 N95739027 ** NOT TESTED ** 343 343 N95739473 ** NOT TESTED ** 344 344 N99320245 ** NOT TESTED ** 345 345 N95739373 ** NOT TESTED ** 346 346 GND GND 347 347 GND GND 348 348 VCORE ** NOT TESTED ** 349 349 GND GND 350 350 VCORE ** NOT TESTED ** 351 351 GND GND 352 352 VCORE ** NOT TESTED ** 353 353 VCORE ** NOT TESTED ** 354 354 GND GND 355 355 VCORE ** NOT TESTED ** 356 356 GND GND 357 357 VCORE ** NOT TESTED ** 358 358 GND GND 359 359 VCORE ** NOT TESTED ** 360 360 GND GND 361 361 VCORE ** NOT TESTED ** 362 362 GND GND 363 363 VCORE ** NOT TESTED ** 364 364 N95876428 ** NOT TESTED ** 365 365 GND GND 366 366 N95876428 ** NOT TESTED ** 367 367 GND GND 368 368 VCCGT ** NOT TESTED ** 369 369 GND GND 370 370 VCCGT ** NOT TESTED ** 371 371 GND GND 372 372 VCCGT ** NOT TESTED ** 373 373 H_X16_SL1_TXP10 ** NOT TESTED ** 374 374 H_X16_SL1_TXN10 ** NOT TESTED ** 375 375 GND GND 376 376 H_X16_SL1_RXN9 ** NOT TESTED ** 377 377 H_X16_SL1_RXP9 ** NOT TESTED ** 378 378 GND GND 379 379 H_PEG_RCOMP ** NOT TESTED ** 380 380 N95738973 ** NOT TESTED ** 381 381 GND GND 382 382 N95739030 ** NOT TESTED ** 383 383 GND GND 384 384 N99320231 ** NOT TESTED ** 385 385 GND GND 386 386 VCORE ** NOT TESTED ** 387 387 VCORE ** NOT TESTED ** 388 388 VCORE ** NOT TESTED ** 389 389 VCORE ** NOT TESTED ** 390 390 VCORE ** NOT TESTED ** 391 391 VCORE ** NOT TESTED ** 392 392 VCORE ** NOT TESTED ** 393 393 VCORE ** NOT TESTED ** 394 394 VCORE ** NOT TESTED ** 395 395 VCORE ** NOT TESTED ** 396 396 VCORE ** NOT TESTED ** 397 397 VCORE ** NOT TESTED ** 398 398 VCORE ** NOT TESTED ** 399 399 VCORE ** NOT TESTED ** 400 400 VCORE ** NOT TESTED ** 401 401 VCORE ** NOT TESTED ** 402 402 VCORE ** NOT TESTED ** 403 403 N95876428 ** NOT TESTED ** 404 404 GND GND 405 405 N95876428 ** NOT TESTED ** 406 406 VCCGT ** NOT TESTED ** 407 407 VCCGT ** NOT TESTED ** 408 408 VCCGT ** NOT TESTED ** 409 409 VCCGT ** NOT TESTED ** 410 410 VCCGT ** NOT TESTED ** 411 411 VCCGT ** NOT TESTED ** 412 412 VCCGT ** NOT TESTED ** 413 413 GND GND 414 414 H_X16_SL1_TXP11 ** NOT TESTED ** 415 415 H_X16_SL1_TXN11 ** NOT TESTED ** 416 416 GND GND 417 417 H_X16_SL1_RXN10 ** NOT TESTED ** 418 418 H_X16_SL1_RXP10 ** NOT TESTED ** 419 419 GND GND 420 420 VCCIO ** NOT TESTED ** 421 421 H_DP_RCOMP ** NOT TESTED ** 422 422 GND GND 423 423 H_CFG_RCOMP ** NOT TESTED ** 424 424 GND GND 425 425 VCORE ** NOT TESTED ** 426 426 VCORE ** NOT TESTED ** 427 427 GND GND 428 428 VCORE ** NOT TESTED ** 429 429 GND GND 430 430 VCORE ** NOT TESTED ** 431 431 GND GND 432 432 VCORE ** NOT TESTED ** 433 433 GND GND 434 434 VCORE ** NOT TESTED ** 435 435 GND GND 436 436 VCORE ** NOT TESTED ** 437 437 GND GND 438 438 VCORE ** NOT TESTED ** 439 439 GND GND 440 440 VCORE ** NOT TESTED ** 441 441 GND GND 442 442 VCORE ** NOT TESTED ** 443 443 N95876428 ** NOT TESTED ** 444 444 VCCGT ** NOT TESTED ** 445 445 VCCGT ** NOT TESTED ** 446 446 GND GND 447 447 VCCGT ** NOT TESTED ** 448 448 GND GND 449 449 VCCGT ** NOT TESTED ** 450 450 GND GND 451 451 VCCGT ** NOT TESTED ** 452 452 H_X16_SL1_TXP12 ** NOT TESTED ** 453 453 H_X16_SL1_TXN12 ** NOT TESTED ** 454 454 GND GND 455 455 H_X16_SL1_RXN11 ** NOT TESTED ** 456 456 H_X16_SL1_RXP11 ** NOT TESTED ** 457 457 GND GND 458 458 VCCSA ** NOT TESTED ** 459 459 GND GND 460 460 GND GND 461 461 VCCGT ** NOT TESTED ** 462 462 VCCGT ** NOT TESTED ** 463 463 VCCGT ** NOT TESTED ** 464 464 VCCGT ** NOT TESTED ** 465 465 VCCGT ** NOT TESTED ** 466 466 VCCGT ** NOT TESTED ** 467 467 VCCGT ** NOT TESTED ** 468 468 GND GND 469 469 H_X16_SL1_TXP13 ** NOT TESTED ** 470 470 H_X16_SL1_TXN13 ** NOT TESTED ** 471 471 GND GND 472 472 H_X16_SL1_RXN12 ** NOT TESTED ** 473 473 H_X16_SL1_RXP12 ** NOT TESTED ** 474 474 VCCSA ** NOT TESTED ** 475 475 VCCIO ** NOT TESTED ** 476 476 VCCGT ** NOT TESTED ** 477 477 VCCGT ** NOT TESTED ** 478 478 GND GND 479 479 VCCGT ** NOT TESTED ** 480 480 GND GND 481 481 VCCGT ** NOT TESTED ** 482 482 GND GND 483 483 VCCGT ** NOT TESTED ** 484 484 H_X16_SL1_TXN14 ** NOT TESTED ** 485 485 H_X16_SL1_TXP14 ** NOT TESTED ** 486 486 GND GND 487 487 H_X16_SL1_RXN13 ** NOT TESTED ** 488 488 H_X16_SL1_RXP13 ** NOT TESTED ** 489 489 GND GND 490 490 VCCSA ** NOT TESTED ** 491 491 GND GND 492 492 GND GND 493 493 VCCGT ** NOT TESTED ** 494 494 VCCGT ** NOT TESTED ** 495 495 VCCGT ** NOT TESTED ** 496 496 VCCGT ** NOT TESTED ** 497 497 VCCGT ** NOT TESTED ** 498 498 VCCGT ** NOT TESTED ** 499 499 VCCGT ** NOT TESTED ** 500 500 GND GND 501 501 H_X16_SL1_TXP15 ** NOT TESTED ** 502 502 H_X16_SL1_TXN15 ** NOT TESTED ** 503 503 GND GND 504 504 H_X16_SL1_RXN14 ** NOT TESTED ** 505 505 H_X16_SL1_RXP14 ** NOT TESTED ** 506 506 VCCSA ** NOT TESTED ** 507 507 VCCIO ** NOT TESTED ** 508 508 VCCGT ** NOT TESTED ** 509 509 VCCGT ** NOT TESTED ** 510 510 GND GND 511 511 VCCGT ** NOT TESTED ** 512 512 GND GND 513 513 VCCGT ** NOT TESTED ** 514 514 GND GND 515 515 VCCGT ** NOT TESTED ** 516 516 H_HDA_SDI_R ** NOT TESTED ** 517 517 S_VCCST_PWRGD ** NOT TESTED ** 518 518 GND GND 519 519 H_X16_SL1_RXN15 ** NOT TESTED ** 520 520 H_X16_SL1_RXP15 ** NOT TESTED ** 521 521 GND GND 522 522 VCCSA ** NOT TESTED ** 523 523 VCCIO ** NOT TESTED ** 524 524 GND GND 525 525 VCCGT ** NOT TESTED ** 526 526 VCCGT ** NOT TESTED ** 527 527 VCCGT ** NOT TESTED ** 528 528 VCCGT ** NOT TESTED ** 529 529 VCCGT ** NOT TESTED ** 530 530 VCCGT ** NOT TESTED ** 531 531 VCCGT ** NOT TESTED ** 532 532 GND GND 533 533 S_HDA_SDO_R ** NOT TESTED ** 534 534 S_HDA_SCLK ** NOT TESTED ** 535 535 VCCST_VCCSFR ** NOT TESTED ** 536 536 VCCST_VCCSFR ** NOT TESTED ** 537 537 VCCST_VCCSFR ** NOT TESTED ** 538 538 VCCSA ** NOT TESTED ** 539 539 GND GND 540 540 VCCGT ** NOT TESTED ** 541 541 VCCGT ** NOT TESTED ** 542 542 GND GND 543 543 VCCGT ** NOT TESTED ** 544 544 GND GND 545 545 VCCGT ** NOT TESTED ** 546 546 P_CPU_GND_GT ** NOT TESTED ** 547 547 VCCGT ** NOT TESTED ** 548 548 CK_100M_PCIBCLKP ** NOT TESTED ** 549 549 CK_100M_PCIBCLKN ** NOT TESTED ** 550 550 GND GND 551 551 CK_100M_CPUIN ** NOT TESTED ** 552 552 CK_100M_CPUIP ** NOT TESTED ** 553 553 GND GND 554 554 VCCSA ** NOT TESTED ** 555 555 VCCIO ** NOT TESTED ** 556 556 GND GND 557 557 VCCGT ** NOT TESTED ** 558 558 VCCGT ** NOT TESTED ** 559 559 VCCGT ** NOT TESTED ** 560 560 VCCGT ** NOT TESTED ** 561 561 VCCGT ** NOT TESTED ** 562 562 H_DMI_RXP0 ** NOT TESTED ** 563 563 H_DMI_RXN0 ** NOT TESTED ** 564 564 GND GND 565 565 VCCSA ** NOT TESTED ** 566 566 VCCSA ** NOT TESTED ** 567 567 VCCSA ** NOT TESTED ** 568 568 VCCGT ** NOT TESTED ** 569 569 VCCGT ** NOT TESTED ** 570 570 GND GND 571 571 VCCGT ** NOT TESTED ** 572 572 GND GND 573 573 VCCGT ** NOT TESTED ** 574 574 GND GND 575 575 H_DMI_RXP1 ** NOT TESTED ** 576 576 H_DMI_RXN1 ** NOT TESTED ** 577 577 VCCSA ** NOT TESTED ** 578 578 VCCSA ** NOT TESTED ** 579 579 GND GND 580 580 GND GND 581 581 VCCGT ** NOT TESTED ** 582 582 VCCGT ** NOT TESTED ** 583 583 VCCGT ** NOT TESTED ** 584 584 VCCGT ** NOT TESTED ** 585 585 VCCGT ** NOT TESTED ** 586 586 H_DMI_RXN2 ** NOT TESTED ** 587 587 H_DMI_RXP2 ** NOT TESTED ** 588 588 GND GND 589 589 VCCSA ** NOT TESTED ** 590 590 VCCSA ** NOT TESTED ** 591 591 VCCSA ** NOT TESTED ** 592 592 VCCGT ** NOT TESTED ** 593 593 VCCGT ** NOT TESTED ** 594 594 H_SKTOCC_ ** NOT TESTED ** 595 595 H_SKL_CNL__R ** NOT TESTED ** 596 596 +1_8V_A_EDRAM ** NOT TESTED ** 597 597 EDRAM_FUSEPRG ** NOT TESTED ** 598 598 GND GND 599 599 H_D3_VREFCA ** NOT TESTED ** 600 600 H_DMI_TXN0 ** NOT TESTED ** 601 601 H_DMI_TXP0 ** NOT TESTED ** 602 602 GND GND 603 603 H_DMI_RXP3 ** NOT TESTED ** 604 604 H_DMI_RXN3 ** NOT TESTED ** 605 605 GND GND 606 606 VCCSA ** NOT TESTED ** 607 607 VCCSA ** NOT TESTED ** 608 608 GND GND 609 609 GND GND 610 610 GND GND 611 611 H_DDR_VTT_CNTL ** NOT TESTED ** 612 612 N96053538 ** NOT TESTED ** 613 613 H_ZVM_ ** NOT TESTED ** 614 614 H_D3B_VREFDQ_R ** NOT TESTED ** 615 615 H_D3A_VREFDQ_R ** NOT TESTED ** 616 616 GND GND 617 617 H_DMI_TXN1 ** NOT TESTED ** 618 618 H_DMI_TXP1 ** NOT TESTED ** 619 619 GND GND 620 620 H_VCCSA_VCC_SENSE ** NOT TESTED ** 621 621 GND GND 622 622 GND GND 623 623 GND GND 624 624 GND GND 625 625 H_D3B_DQ4 ** NOT TESTED ** 626 626 H_D3B_DQ5 ** NOT TESTED ** 627 627 GND GND 628 628 GND GND 629 629 GND GND 630 630 GND GND 631 631 GND GND 632 632 H_DMI_TXN2 ** NOT TESTED ** 633 633 H_DMI_TXP2 ** NOT TESTED ** 634 634 GND GND 635 635 H_SAIO_VSS_SENSE GND* 636 636 GND GND 637 637 H_D3B_DQ63 ** NOT TESTED ** 638 638 H_D3B_DQ59 ** NOT TESTED ** 639 639 GND GND 640 640 GND GND 641 641 H_D3B_DQ0 ** NOT TESTED ** 642 642 H_D3B_DQ1 ** NOT TESTED ** 643 643 GND GND 644 644 H_D3A_DQ1 ** NOT TESTED ** 645 645 H_D3A_DQ5 ** NOT TESTED ** 646 646 H_D3A_DQ4 ** NOT TESTED ** 647 647 H_D3A_DQ0 ** NOT TESTED ** 648 648 GND GND 649 649 H_DMI_TXP3 ** NOT TESTED ** 650 650 H_DMI_TXN3 ** NOT TESTED ** 651 651 H_VCCIO_VCC_SENSE ** NOT TESTED ** 652 652 GND GND 653 653 H_D3B_DQ62 ** NOT TESTED ** 654 654 H_D3B_DQ58 ** NOT TESTED ** 655 655 GND GND 656 656 GND GND 657 657 H_D3B_DQSN0 ** NOT TESTED ** 658 658 H_D3B_DQSP0 ** NOT TESTED ** 659 659 GND GND 660 660 GND GND 661 661 H_D3A_DQSP0 ** NOT TESTED ** 662 662 H_D3A_DQSN0 ** NOT TESTED ** 663 663 GND GND 664 664 GND GND 665 665 GND GND 666 666 GND GND 667 667 GND GND 668 668 GND GND 669 669 H_D3B_DQSN7 ** NOT TESTED ** 670 670 H_D3B_DQSP7 ** NOT TESTED ** 671 671 GND GND 672 672 GND GND 673 673 H_D3B_DQ6 ** NOT TESTED ** 674 674 H_D3B_DQ7 ** NOT TESTED ** 675 675 GND GND 676 676 H_D3A_DQ3 ** NOT TESTED ** 677 677 H_D3A_DQ2 ** NOT TESTED ** 678 678 H_D3A_DQ6 ** NOT TESTED ** 679 679 H_D3A_DQ7 ** NOT TESTED ** 680 680 H_D3A_DQ63 ** NOT TESTED ** 681 681 H_D3A_DQ59 ** NOT TESTED ** 682 682 H_D3A_DQ58 ** NOT TESTED ** 683 683 H_D3A_DQ62 ** NOT TESTED ** 684 684 GND GND 685 685 H_D3B_DQ57 ** NOT TESTED ** 686 686 H_D3B_DQ60 ** NOT TESTED ** 687 687 GND GND 688 688 GND GND 689 689 H_D3B_DQ2 ** NOT TESTED ** 690 690 H_D3B_DQ3 ** NOT TESTED ** 691 691 GND GND 692 692 GND GND 693 693 GND GND 694 694 GND GND 695 695 GND GND 696 696 GND GND 697 697 H_D3A_DQSP7 ** NOT TESTED ** 698 698 H_D3A_DQSN7 ** NOT TESTED ** 699 699 GND GND 700 700 GND GND 701 701 H_D3B_DQ61 ** NOT TESTED ** 702 702 H_D3B_DQ56 ** NOT TESTED ** 703 703 GND GND 704 704 VDDQ ** NOT TESTED ** 705 705 VCORE ** NOT TESTED ** 706 706 VCORE ** NOT TESTED ** 707 707 VCORE ** NOT TESTED ** 708 708 VCORE ** NOT TESTED ** 709 709 VCORE ** NOT TESTED ** 710 710 VCORE ** NOT TESTED ** 711 711 VCORE ** NOT TESTED ** 712 712 VCORE ** NOT TESTED ** 713 713 VCORE ** NOT TESTED ** 714 714 VCORE ** NOT TESTED ** 715 715 VCORE ** NOT TESTED ** 716 716 VCORE ** NOT TESTED ** 717 717 VCCIO ** NOT TESTED ** 718 718 N97039428 ** NOT TESTED ** 719 719 VCC_EOPIO ** NOT TESTED ** 720 720 VCC_EOPIO ** NOT TESTED ** 721 721 VCC_EDRAM ** NOT TESTED ** 722 722 VCC_EDRAM ** NOT TESTED ** 723 723 VCC_EDRAM ** NOT TESTED ** 724 724 VCC_EDRAM ** NOT TESTED ** 725 725 GND GND 726 726 GND GND 727 727 GND GND 728 728 GND GND 729 729 GND GND 730 730 GND GND 731 731 H_D3A_DQ9 ** NOT TESTED ** 732 732 H_D3A_DQ13 ** NOT TESTED ** 733 733 H_D3A_DQ12 ** NOT TESTED ** 734 734 H_D3A_DQ8 ** NOT TESTED ** 735 735 H_D3A_DQ56 ** NOT TESTED ** 736 736 H_D3A_DQ57 ** NOT TESTED ** 737 737 H_D3A_DQ61 ** NOT TESTED ** 738 738 H_D3A_DQ60 ** NOT TESTED ** 739 739 GND GND 740 740 GND GND 741 741 GND GND 742 742 GND GND 743 743 GND GND 744 744 GND GND 745 745 VCCIO ** NOT TESTED ** 746 746 GND GND 747 747 GND GND 748 748 VCCIO ** NOT TESTED ** 749 749 GND GND 750 750 GND GND 751 751 GND GND 752 752 GND GND 753 753 GND GND 754 754 GND GND 755 755 N97039456 ** NOT TESTED ** 756 756 N97039433 ** NOT TESTED ** 757 757 GND GND 758 758 VCCIO ** NOT TESTED ** 759 759 GND GND 760 760 GND GND 761 761 VCC_EDRAM ** NOT TESTED ** 762 762 GND GND 763 763 GND GND 764 764 GND GND 765 765 H_D3B_DQ10 ** NOT TESTED ** 766 766 H_D3B_DQ14 ** NOT TESTED ** 767 767 H_D3B_DQSN1 ** NOT TESTED ** 768 768 H_D3B_DQ12 ** NOT TESTED ** 769 769 H_D3B_DQ13 ** NOT TESTED ** 770 770 GND GND 771 771 GND GND 772 772 H_D3A_DQSP1 ** NOT TESTED ** 773 773 H_D3A_DQSN1 ** NOT TESTED ** 774 774 GND GND 775 775 GND GND 776 776 GND GND 777 777 GND GND 778 778 GND GND 779 779 GND GND 780 780 H_D3B_DQ50 ** NOT TESTED ** 781 781 H_D3B_DQ51 ** NOT TESTED ** 782 782 H_D3B_DQSP6 ** NOT TESTED ** 783 783 H_D3B_DQ49 ** NOT TESTED ** 784 784 H_D3B_DQ53 ** NOT TESTED ** 785 785 GND GND 786 786 H_D3B_DQ35 ** NOT TESTED ** 787 787 H_D3B_DQ34 ** NOT TESTED ** 788 788 GND GND 789 789 H_D3B_ODT3 ** NOT TESTED ** 790 790 H_D3B_ODT1 ** NOT TESTED ** 791 791 H_D3B_WE_ ** NOT TESTED ** 792 792 H_D3B_BA0 ** NOT TESTED ** 793 793 H_D3B_MA0 ** NOT TESTED ** 794 794 N60799314 ** NOT TESTED ** 795 795 GND GND 796 796 H_D3B_MA1 ** NOT TESTED ** 797 797 H_D3B_MA5 ** NOT TESTED ** 798 798 GND GND 799 799 NC_2139 NC 800 800 NC_2140 NC 801 801 GND GND 802 802 H_D3B_DQ29 ** NOT TESTED ** 803 803 H_D3B_DQ28 ** NOT TESTED ** 804 804 GND GND 805 805 H_D3B_DQ11 ** NOT TESTED ** 806 806 H_D3B_DQ15 ** NOT TESTED ** 807 807 H_D3B_DQSP1 ** NOT TESTED ** 808 808 H_D3B_DQ8 ** NOT TESTED ** 809 809 H_D3B_DQ9 ** NOT TESTED ** 810 810 GND GND 811 811 H_D3A_DQ11 ** NOT TESTED ** 812 812 H_D3A_DQ10 ** NOT TESTED ** 813 813 H_D3A_DQ14 ** NOT TESTED ** 814 814 H_D3A_DQ15 ** NOT TESTED ** 815 815 H_D3A_DQ55 ** NOT TESTED ** 816 816 H_D3A_DQ51 ** NOT TESTED ** 817 817 H_D3A_DQ50 ** NOT TESTED ** 818 818 H_D3A_DQ54 ** NOT TESTED ** 819 819 GND GND 820 820 H_D3B_DQ54 ** NOT TESTED ** 821 821 H_D3B_DQ55 ** NOT TESTED ** 822 822 H_D3B_DQSN6 ** NOT TESTED ** 823 823 H_D3B_DQ48 ** NOT TESTED ** 824 824 H_D3B_DQ52 ** NOT TESTED ** 825 825 GND GND 826 826 H_D3B_DQ39 ** NOT TESTED ** 827 827 H_D3B_DQ38 ** NOT TESTED ** 828 828 GND GND 829 829 H_D3B_CS_3 ** NOT TESTED ** 830 830 H_D3B_ODT0 ** NOT TESTED ** 831 831 GND GND 832 832 H_D3B_BA1 ** NOT TESTED ** 833 833 GND GND 834 834 H_D3B_CLKP0 ** NOT TESTED ** 835 835 H_D3B_CLKN0 ** NOT TESTED ** 836 836 H_D3B_MA2 ** NOT TESTED ** 837 837 H_D3B_MA3 ** NOT TESTED ** 838 838 GND GND 839 839 NC_2141 NC 840 840 NC_2142 NC 841 841 GND GND 842 842 H_D3B_DQ25 ** NOT TESTED ** 843 843 H_D3B_DQ24 ** NOT TESTED ** 844 844 GND GND 845 845 GND GND 846 846 GND GND 847 847 GND GND 848 848 GND GND 849 849 GND GND 850 850 GND GND 851 851 GND GND 852 852 GND GND 853 853 GND GND 854 854 GND GND 855 855 GND GND 856 856 H_D3A_DQSP6 ** NOT TESTED ** 857 857 H_D3A_DQSN6 ** NOT TESTED ** 858 858 GND GND 859 859 GND GND 860 860 GND GND 861 861 GND GND 862 862 GND GND 863 863 GND GND 864 864 GND GND 865 865 GND GND 866 866 H_D3B_DQSP4 ** NOT TESTED ** 867 867 H_D3B_DQSN4 ** NOT TESTED ** 868 868 GND GND 869 869 H_D3B_CS_1 ** NOT TESTED ** 870 870 GND GND 871 871 H_D3B_CS_2 ** NOT TESTED ** 872 872 H_D3B_RAS_ ** NOT TESTED ** 873 873 GND GND 874 874 H_D3B_CLKP2 ** NOT TESTED ** 875 875 H_D3B_CLKN2 ** NOT TESTED ** 876 876 GND GND 877 877 GND GND 878 878 GND GND 879 879 NC_2143 NC 880 880 NC_2144 NC 881 881 GND GND 882 882 H_D3B_DQSP3 ** NOT TESTED ** 883 883 H_D3B_DQSN3 ** NOT TESTED ** 884 884 GND GND 885 885 H_D3B_DQ18 ** NOT TESTED ** 886 886 H_D3B_DQ22 ** NOT TESTED ** 887 887 H_D3B_DQSN2 ** NOT TESTED ** 888 888 H_D3B_DQ17 ** NOT TESTED ** 889 889 H_D3B_DQ20 ** NOT TESTED ** 890 890 GND GND 891 891 H_D3A_DQ17 ** NOT TESTED ** 892 892 H_D3A_DQ21 ** NOT TESTED ** 893 893 H_D3A_DQ20 ** NOT TESTED ** 894 894 H_D3A_DQ16 ** NOT TESTED ** 895 895 H_D3A_DQ48 ** NOT TESTED ** 896 896 H_D3A_DQ49 ** NOT TESTED ** 897 897 H_D3A_DQ53 ** NOT TESTED ** 898 898 H_D3A_DQ52 ** NOT TESTED ** 899 899 GND GND 900 900 H_D3B_DQ43 ** NOT TESTED ** 901 901 H_D3B_DQ42 ** NOT TESTED ** 902 902 H_D3B_DQSP5 ** NOT TESTED ** 903 903 H_D3B_DQ40 ** NOT TESTED ** 904 904 H_D3B_DQ44 ** NOT TESTED ** 905 905 GND GND 906 906 H_D3B_DQ33 ** NOT TESTED ** 907 907 H_D3B_DQ37 ** NOT TESTED ** 908 908 GND GND 909 909 H_D3B_ODT2 ** NOT TESTED ** 910 910 H_D3B_CAS_ ** NOT TESTED ** 911 911 H_D3B_CS_0 ** NOT TESTED ** 912 912 H_D3B_MA10 ** NOT TESTED ** 913 913 H_D3B_CLKP3 ** NOT TESTED ** 914 914 H_D3B_CLKN3 ** NOT TESTED ** 915 915 H_D3B_CLKN1 ** NOT TESTED ** 916 916 H_D3B_CLKP1 ** NOT TESTED ** 917 917 H_D3B_MA4 ** NOT TESTED ** 918 918 GND GND 919 919 NC_2145 NC 920 920 NC_2146 NC 921 921 GND GND 922 922 H_D3B_DQ31 ** NOT TESTED ** 923 923 H_D3B_DQ30 ** NOT TESTED ** 924 924 GND GND 925 925 H_D3B_DQ19 ** NOT TESTED ** 926 926 H_D3B_DQ23 ** NOT TESTED ** 927 927 H_D3B_DQSP2 ** NOT TESTED ** 928 928 H_D3B_DQ21 ** NOT TESTED ** 929 929 H_D3B_DQ16 ** NOT TESTED ** 930 930 GND GND 931 931 GND GND 932 932 H_D3A_DQSP2 ** NOT TESTED ** 933 933 H_D3A_DQSN2 ** NOT TESTED ** 934 934 GND GND 935 935 GND GND 936 936 GND GND 937 937 GND GND 938 938 GND GND 939 939 GND GND 940 940 H_D3B_DQ47 ** NOT TESTED ** 941 941 H_D3B_DQ46 ** NOT TESTED ** 942 942 H_D3B_DQSN5 ** NOT TESTED ** 943 943 H_D3B_DQ41 ** NOT TESTED ** 944 944 H_D3B_DQ45 ** NOT TESTED ** 945 945 GND GND 946 946 H_D3B_DQ32 ** NOT TESTED ** 947 947 H_D3B_DQ36 ** NOT TESTED ** 948 948 GND GND 949 949 H_D3B_MA13 ** NOT TESTED ** 950 950 GND GND 951 951 GND GND 952 952 GND GND 953 953 GND GND 954 954 GND GND 955 955 GND GND 956 956 GND GND 957 957 GND GND 958 958 GND GND 959 959 NC_2147 NC 960 960 NC_2148 NC 961 961 GND GND 962 962 H_D3B_DQ27 ** NOT TESTED ** 963 963 H_D3B_DQ26 ** NOT TESTED ** 964 964 GND GND 965 965 GND GND 966 966 GND GND 967 967 GND GND 968 968 GND GND 969 969 GND GND 970 970 GND GND 971 971 H_D3A_DQ19 ** NOT TESTED ** 972 972 H_D3A_DQ18 ** NOT TESTED ** 973 973 H_D3A_DQ22 ** NOT TESTED ** 974 974 H_D3A_DQ23 ** NOT TESTED ** 975 975 H_D3A_DQ47 ** NOT TESTED ** 976 976 H_D3A_DQ43 ** NOT TESTED ** 977 977 H_D3A_DQ42 ** NOT TESTED ** 978 978 H_D3A_DQ46 ** NOT TESTED ** 979 979 GND GND 980 980 GND GND 981 981 GND GND 982 982 GND GND 983 983 GND GND 984 984 GND GND 985 985 GND GND 986 986 GND GND 987 987 GND GND 988 988 GND GND 989 989 GND GND 990 990 H_D3A_CLKP3 ** NOT TESTED ** 991 991 GND GND 992 992 VDDQ ** NOT TESTED ** 993 993 H_D3A_MA4 ** NOT TESTED ** 994 994 H_D3A_MA8 ** NOT TESTED ** 995 995 VDDQ ** NOT TESTED ** 996 996 H_D3A_MA9 ** NOT TESTED ** 997 997 GND GND 998 998 GND GND 999 999 GND GND 1000 1000 GND GND 1001 1001 GND GND 1002 1002 GND GND 1003 1003 GND GND 1004 1004 GND GND 1005 1005 GND GND 1006 1006 GND GND 1007 1007 NC_2149 NC 1008 1008 GND GND 1009 1009 H_D3A_DQ30 ** NOT TESTED ** 1010 1010 GND GND 1011 1011 GND GND 1012 1012 GND GND 1013 1013 GND GND 1014 1014 GND GND 1015 1015 GND GND 1016 1016 H_D3A_DQSP5 ** NOT TESTED ** 1017 1017 H_D3A_DQSN5 ** NOT TESTED ** 1018 1018 GND GND 1019 1019 GND GND 1020 1020 H_D3A_DQ35 ** NOT TESTED ** 1021 1021 GND GND 1022 1022 H_D3A_DQ33 ** NOT TESTED ** 1023 1023 N95739247 ** NOT TESTED ** 1024 1024 N95739250 ** NOT TESTED ** 1025 1025 H_D3A_CS_1 ** NOT TESTED ** 1026 1026 H_D3A_ODT2 ** NOT TESTED ** 1027 1027 VDDQ ** NOT TESTED ** 1028 1028 H_D3A_ODT1 ** NOT TESTED ** 1029 1029 VDDQ ** NOT TESTED ** 1030 1030 H_D3A_CLKN3 ** NOT TESTED ** 1031 1031 H_D3A_MA2 ** NOT TESTED ** 1032 1032 H_D3A_MA1 ** NOT TESTED ** 1033 1033 VDDQ ** NOT TESTED ** 1034 1034 H_D3A_MA5 ** NOT TESTED ** 1035 1035 H_D3A_MA7 ** NOT TESTED ** 1036 1036 H_D3A_MA11 ** NOT TESTED ** 1037 1037 VDDQ ** NOT TESTED ** 1038 1038 H_D3A_MA15 ** NOT TESTED ** 1039 1039 GND GND 1040 1040 H_D3B_MA8 ** NOT TESTED ** 1041 1041 H_D3B_MA11 ** NOT TESTED ** 1042 1042 H_D3B_MA15 ** NOT TESTED ** 1043 1043 H_D3B_CKE3 ** NOT TESTED ** 1044 1044 GND GND 1045 1045 NC_2150 NC 1046 1046 NC_2151 NC 1047 1047 NC_2152 NC 1048 1048 GND GND 1049 1049 H_D3A_DQ26 ** NOT TESTED ** 1050 1050 H_D3A_DQSN3 ** NOT TESTED ** 1051 1051 H_D3A_DQ29 ** NOT TESTED ** 1052 1052 H_D3A_DQ28 ** NOT TESTED ** 1053 1053 NC_2153 NC 1054 1054 NC_2154 NC 1055 1055 NC_2155 NC 1056 1056 GND GND 1057 1057 H_D3A_DQ41 ** NOT TESTED ** 1058 1058 H_D3A_DQ40 ** NOT TESTED ** 1059 1059 GND GND 1060 1060 H_D3A_DQ34 ** NOT TESTED ** 1061 1061 H_D3A_DQSP4 ** NOT TESTED ** 1062 1062 H_D3A_DQ37 ** NOT TESTED ** 1063 1063 GND GND 1064 1064 H_D3A_CS_3 ** NOT TESTED ** 1065 1065 VDDQ ** NOT TESTED ** 1066 1066 H_D3A_MA13 ** NOT TESTED ** 1067 1067 H_D3A_CS_2 ** NOT TESTED ** 1068 1068 H_D3A_WE_ ** NOT TESTED ** 1069 1069 H_D3A_BA1 ** NOT TESTED ** 1070 1070 H_D3A_CLKN2 ** NOT TESTED ** 1071 1071 VDDQ ** NOT TESTED ** 1072 1072 H_D3A_CLKN0 ** NOT TESTED ** 1073 1073 H_D3A_MA3 ** NOT TESTED ** 1074 1074 H_D3A_MA6 ** NOT TESTED ** 1075 1075 VDDQ ** NOT TESTED ** 1076 1076 H_D3A_MA12 ** NOT TESTED ** 1077 1077 H_D3A_MA14 ** NOT TESTED ** 1078 1078 H_D3A_CKE2 ** NOT TESTED ** 1079 1079 H_D3A_CKE3 ** NOT TESTED ** 1080 1080 GND GND 1081 1081 H_D3B_MA12 ** NOT TESTED ** 1082 1082 GND GND 1083 1083 H_D3B_CKE1 ** NOT TESTED ** 1084 1084 GND GND 1085 1085 NC_2156 NC 1086 1086 NC_2157 NC 1087 1087 NC_2158 NC 1088 1088 GND GND 1089 1089 H_D3A_DQ27 ** NOT TESTED ** 1090 1090 H_D3A_DQSP3 ** NOT TESTED ** 1091 1091 H_D3A_DQ24 ** NOT TESTED ** 1092 1092 GND GND 1093 1093 NC_2159 NC 1094 1094 NC_2160 NC 1095 1095 GND GND 1096 1096 H_D3A_DQ45 ** NOT TESTED ** 1097 1097 GND GND 1098 1098 H_D3A_DQ39 ** NOT TESTED ** 1099 1099 H_D3A_DQSN4 ** NOT TESTED ** 1100 1100 H_D3A_DQ36 ** NOT TESTED ** 1101 1101 GND GND 1102 1102 VDDQ ** NOT TESTED ** 1103 1103 H_D3A_ODT0 ** NOT TESTED ** 1104 1104 H_D3A_CS_0 ** NOT TESTED ** 1105 1105 H_D3A_RAS_ ** NOT TESTED ** 1106 1106 VDDQ ** NOT TESTED ** 1107 1107 H_D3A_MA0 ** NOT TESTED ** 1108 1108 H_D3A_CLKP2 ** NOT TESTED ** 1109 1109 H_D3A_CLKP1 ** NOT TESTED ** 1110 1110 H_D3A_CLKP0 ** NOT TESTED ** 1111 1111 H_D3A_BA2 ** NOT TESTED ** 1112 1112 H_D3A_CKE1 ** NOT TESTED ** 1113 1113 VDDQ ** NOT TESTED ** 1114 1114 H_D3B_MA6 ** NOT TESTED ** 1115 1115 H_D3B_MA9 ** NOT TESTED ** 1116 1116 H_D3B_BA2 ** NOT TESTED ** 1117 1117 H_D3B_CKE2 ** NOT TESTED ** 1118 1118 GND GND 1119 1119 NC_2161 NC 1120 1120 GND GND 1121 1121 NC_2162 NC 1122 1122 GND GND 1123 1123 H_D3A_DQ31 ** NOT TESTED ** 1124 1124 GND GND 1125 1125 H_D3A_DQ25 ** NOT TESTED ** 1126 1126 NC_2163 NC 1127 1127 GND GND 1128 1128 H_D3A_DQ44 ** NOT TESTED ** 1129 1129 GND GND 1130 1130 H_D3A_DQ38 ** NOT TESTED ** 1131 1131 GND GND 1132 1132 H_D3A_DQ32 ** NOT TESTED ** 1133 1133 GND GND 1134 1134 H_D3A_ODT3 ** NOT TESTED ** 1135 1135 H_D3A_CAS_ ** NOT TESTED ** 1136 1136 VDDQ ** NOT TESTED ** 1137 1137 H_D3A_BA0 ** NOT TESTED ** 1138 1138 H_D3A_MA10 ** NOT TESTED ** 1139 1139 N60798268 ** NOT TESTED ** 1140 1140 VDDQ ** NOT TESTED ** 1141 1141 H_D3A_CLKN1 ** NOT TESTED ** 1142 1142 VDDQ ** NOT TESTED ** 1143 1143 VDDQ ** NOT TESTED ** 1144 1144 H_D3A_CKE0 ** NOT TESTED ** 1145 1145 GND GND 1146 1146 H_D3B_MA7 ** NOT TESTED ** 1147 1147 GND GND 1148 1148 H_D3B_MA14 ** NOT TESTED ** 1149 1149 H_D3B_CKE0 ** NOT TESTED ** 1150 1150 GND GND 1151 1151 NC_2164 NC _____________________________________________________________________________________________________________________________________________________ Totals 382 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 0.0 Testable Pins = 733 UnTested Pins = 733 Analog Coverage = 0.0 Analog Tested Pins = 0 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #22 UO2U1 Loc:C3 Side:T TotalPin:21 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 O2_PWRGD__B ** NOT TESTED ** 2 2 O2_ADFC_2 ** NOT TESTED ** 3 3 O2_ADFC_1 ** NOT TESTED ** 4 4 +3V_VDDIN VCC 5 5 O2_HW_SEL ** NOT TESTED ** 6 6 O2_VCO_SEL ** NOT TESTED ** 7 7 O2_RESET_ ** NOT TESTED ** 8 8 NC_1809 NC 9 9 GND GND 10 10 +3V_VDDIN VCC 11 11 CK_100M_C ** NOT TESTED ** 12 12 CK_100M_T ** NOT TESTED ** 13 13 GND GND 14 14 O2_SMB1_CLK ** NOT TESTED ** 15 15 O2_SMB1_DATA ** NOT TESTED ** 16 16 +3V_VDDIN VCC 17 17 C_CPU1_ ** NOT TESTED ** 18 18 C_CPU1 ** NOT TESTED ** 19 19 GND GND 20 20 O2_SEL_CLK ** NOT TESTED ** 21 21 GND GND _____________________________________________________________________________________________________________________________________________________ Totals 7 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 0.0 Testable Pins = 13 UnTested Pins = 13 Analog Coverage = 0.0 Analog Tested Pins = 0 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #23 UOU1 Loc:B1 Side:T TotalPin:64 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 +3V_O1P1 ** NOT TESTED ** 2 2 O1_PIN2 X 3 3 CK_SIO_IO_R3 X 4 4 CK_24M_SIO_LPC X 5 5 S_SERIRQ ** NOT TESTED ** 6 6 S_LAD3 ** NOT TESTED ** 7 7 S_LAD2 ** NOT TESTED ** 8 8 S_LAD1 ** NOT TESTED ** 9 9 S_LAD0 ** NOT TESTED ** 10 10 +3V VCC 11 11 S_LFRAME_ ** NOT TESTED ** 12 12 S_PLTRST_ ** NOT TESTED ** 13 13 O_GA20 X 14 14 O_KBRST__R X 15 15 O_COM1_CTS1_ ** NOT TESTED ** 16 16 O_COM1_DSR1_ ** NOT TESTED ** 17 17 O_COM1_RTS1_ ** NOT TESTED ** 18 18 O_COM1_DTR1_ ** NOT TESTED ** 19 19 O_COM1_RXD1 ** NOT TESTED ** 20 20 O_COM1_TXD1 ** NOT TESTED ** 21 21 O_COM1_DCD1_ ** NOT TESTED ** 22 22 LAN_SIO_WAKE_ ** NOT TESTED ** 23 23 O1_RSTCON__R X 24 24 +3VSB_ATX ** NOT TESTED ** 25 25 O_MS_CLK X 26 26 O_MS_DATA X 27 27 O_KB_CLK X 28 28 O_KB_DATA X 29 29 O1_IOPWRBTN__R X 30 30 O_PWRBTN__R X 31 31 O_+1_8VA X 32 32 O_SLP_S3__R X 33 33 O1_PME_ X 34 34 O_DEEP_S5 X 35 35 O_3VSBSW_ X 36 36 O_MEMOK_ X 37 37 O_X1_RST__R X 38 38 O_X16_RST__R X 39 39 O_PWROK_R X 40 40 O_RSTCON__P_R X 41 41 O_SLP_S4__R X 42 42 O1_PIN42 X 43 43 GND GND 44 44 +3V_BAT_2 X 45 45 +3V_BAT_1 X 46 46 O1_P46 X 47 47 O_12V_IN_2 X 48 48 O_5V_IN_2 X 49 49 O_12V_IN_1 X 50 50 O_5V_IN_1 X 51 51 +AVCC_SIO ** NOT TESTED ** 52 52 O_VCORE_IN X 53 53 O_VREF_SIO X 54 54 O_TR_MB X 55 55 H_TR X 56 56 GND GND 57 57 +VTT_O1 X 58 58 O_H_PECI X 59 59 O_CHAFAN_PWM2 X 60 60 NC_1789 NC 61 61 O_CPUFANIN X 62 62 O_CPUFAN_PWM X 63 63 O_CHAFANIN1 X 64 64 O_CHAFAN_PWM X _____________________________________________________________________________________________________________________________________________________ Totals 3 1 42 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 70.0 Testable Pins = 60 UnTested Pins = 18 Analog Coverage = 70.0 Analog Tested Pins = 42 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #24 UO310 Loc:F4 Side:T TotalPin:18 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 CHAFANPWR ** NOT TESTED ** 2 2 +12V VCC 3 3 O_CHAFAN_EN X 4 4 O_CHAFAN_VSET1 X 5 5 GND GND 6 6 GND GND 7 7 GND GND 8 8 GND GND 9 9 GND GND 10 10 GND GND 11 11 GND GND 12 12 GND GND 13 13 GND GND 14 14 GND GND 15 15 GND GND 16 16 GND GND 17 17 GND GND 18 18 GND GND _____________________________________________________________________________________________________________________________________________________ Totals 15 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 66.7 Testable Pins = 3 UnTested Pins = 1 Analog Coverage = 66.7 Analog Tested Pins = 2 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #25 UO320 Loc:B1 Side:T TotalPin:18 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 CHAFANPWR2 ** NOT TESTED ** 2 2 +12V VCC 3 3 O_CHAFAN_EN2 X 4 4 O_CHAFAN_VSET2 X 5 5 GND GND 6 6 GND GND 7 7 GND GND 8 8 GND GND 9 9 GND GND 10 10 GND GND 11 11 GND GND 12 12 GND GND 13 13 GND GND 14 14 GND GND 15 15 GND GND 16 16 GND GND 17 17 GND GND 18 18 GND GND _____________________________________________________________________________________________________________________________________________________ Totals 15 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 66.7 Testable Pins = 3 UnTested Pins = 1 Analog Coverage = 66.7 Analog Tested Pins = 2 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #26 UPCI1 Loc:B2 Side:T TotalPin:122 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 GND GND 2 2 +12V ** NOT TESTED ** 3 3 +5V ** NOT TESTED ** 4 4 +5V ** NOT TESTED ** 5 5 +5V ** NOT TESTED ** 6 6 K_INTA_ ** NOT TESTED ** 7 7 K_INTC_ ** NOT TESTED ** 8 8 +5V ** NOT TESTED ** 9 9 NC_2007 ** NOT TESTED ** 10 10 +5V ** NOT TESTED ** 11 11 NC_2008 ** NOT TESTED ** 12 12 GND GND 13 13 GND GND 14 14 +3VSB ** NOT TESTED ** 15 15 K_PCIRST_ ** NOT TESTED ** 16 16 +5V ** NOT TESTED ** 17 17 K_GNT_0 ** NOT TESTED ** 18 18 GND GND 19 19 K_PME_ ** NOT TESTED ** 20 20 K_AD30 ** NOT TESTED ** 21 21 +3V_ATX ** NOT TESTED ** 22 22 K_AD28 ** NOT TESTED ** 23 23 K_AD26 ** NOT TESTED ** 24 24 GND GND 25 25 K_AD24 ** NOT TESTED ** 26 26 K_AD16 ** NOT TESTED ** 27 27 +3V_ATX ** NOT TESTED ** 28 28 K_AD22 ** NOT TESTED ** 29 29 K_AD20 ** NOT TESTED ** 30 30 GND GND 31 31 K_AD18 ** NOT TESTED ** 32 32 K_AD16 ** NOT TESTED ** 33 33 +3V_ATX ** NOT TESTED ** 34 34 K_FRAME_ ** NOT TESTED ** 35 35 GND GND 36 36 K_TRDY_ ** NOT TESTED ** 37 37 GND GND 38 38 K_STOP_ ** NOT TESTED ** 39 39 +3V_ATX ** NOT TESTED ** 40 40 S_SMBCLK_SLOT ** NOT TESTED ** 41 41 S_SMBDATA_SLOT ** NOT TESTED ** 42 42 GND GND 43 43 K_PAR ** NOT TESTED ** 44 44 K_AD15 ** NOT TESTED ** 45 45 +3V_ATX ** NOT TESTED ** 46 46 K_AD13 ** NOT TESTED ** 47 47 K_AD11 ** NOT TESTED ** 48 48 GND GND 49 49 K_AD9 ** NOT TESTED ** 50 50 K_C_BE_0 ** NOT TESTED ** 51 51 +3V_ATX ** NOT TESTED ** 52 52 K_AD6 ** NOT TESTED ** 53 53 K_AD4 ** NOT TESTED ** 54 54 GND GND 55 55 K_AD2 ** NOT TESTED ** 56 56 K_AD0 ** NOT TESTED ** 57 57 +5V ** NOT TESTED ** 58 58 K_REQ64_ ** NOT TESTED ** 59 59 +5V ** NOT TESTED ** 60 60 +5V ** NOT TESTED ** 61 61 -12V ** NOT TESTED ** 62 62 GND GND 63 63 GND GND 64 64 NC_2009 ** NOT TESTED ** 65 65 +5V ** NOT TESTED ** 66 66 +5V ** NOT TESTED ** 67 67 K_INTB_ ** NOT TESTED ** 68 68 K_INTD_ ** NOT TESTED ** 69 69 NC_2010 ** NOT TESTED ** 70 70 NC_2011 ** NOT TESTED ** 71 71 NC_2012 ** NOT TESTED ** 72 72 GND GND 73 73 GND GND 74 74 NC_2013 ** NOT TESTED ** 75 75 GND GND 76 76 CK_33M_SL1 ** NOT TESTED ** 77 77 GND GND 78 78 K_REQ_0 ** NOT TESTED ** 79 79 +5V ** NOT TESTED ** 80 80 K_AD31 ** NOT TESTED ** 81 81 K_AD29 ** NOT TESTED ** 82 82 GND GND 83 83 K_AD27 ** NOT TESTED ** 84 84 K_AD25 ** NOT TESTED ** 85 85 +3V_ATX ** NOT TESTED ** 86 86 K_C_BE_3 ** NOT TESTED ** 87 87 K_AD23 ** NOT TESTED ** 88 88 GND GND 89 89 K_AD21 ** NOT TESTED ** 90 90 K_AD19 ** NOT TESTED ** 91 91 +3V_ATX ** NOT TESTED ** 92 92 K_AD17 ** NOT TESTED ** 93 93 K_C_BE_2 ** NOT TESTED ** 94 94 GND GND 95 95 K_IRDY_ ** NOT TESTED ** 96 96 +3V_ATX ** NOT TESTED ** 97 97 K_DEVSEL_ ** NOT TESTED ** 98 98 GND GND 99 99 K_LOCK_ ** NOT TESTED ** 100 100 K_PERR_ ** NOT TESTED ** 101 101 +3V_ATX ** NOT TESTED ** 102 102 K_SERR_ ** NOT TESTED ** 103 103 +3V_ATX ** NOT TESTED ** 104 104 K_C_BE_1 ** NOT TESTED ** 105 105 K_AD14 ** NOT TESTED ** 106 106 GND GND 107 107 K_AD12 ** NOT TESTED ** 108 108 K_AD10 ** NOT TESTED ** 109 109 GND GND 110 110 K_AD8 ** NOT TESTED ** 111 111 K_AD7 ** NOT TESTED ** 112 112 +3V_ATX ** NOT TESTED ** 113 113 K_AD5 ** NOT TESTED ** 114 114 K_AD3 ** NOT TESTED ** 115 115 GND GND 116 116 K_AD1 ** NOT TESTED ** 117 117 +5V ** NOT TESTED ** 118 118 +5V ** NOT TESTED ** 119 119 +5V ** NOT TESTED ** 120 120 +5V ** NOT TESTED ** 121 121 NC_2014 NC 122 122 NC_2015 NC _____________________________________________________________________________________________________________________________________________________ Totals 24 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 0.0 Testable Pins = 96 UnTested Pins = 96 Analog Coverage = 0.0 Analog Tested Pins = 0 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #27 UPEX1 Loc:C2 Side:T TotalPin:166 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 GND GND 2 2 +12V ** NOT TESTED ** 3 3 +12V ** NOT TESTED ** 4 4 GND GND 5 5 NC_2041 ** NOT TESTED ** 6 6 NC_2042 ** NOT TESTED ** 7 7 NC_2043 ** NOT TESTED ** 8 8 NC_2044 ** NOT TESTED ** 9 9 +3V_ATX ** NOT TESTED ** 10 10 +3V_ATX ** NOT TESTED ** 11 11 O_X16_RST_ ** NOT TESTED ** 12 12 GND GND 13 13 CK_100M_X16SL1P ** NOT TESTED ** 14 14 CK_100M_X16SL1N ** NOT TESTED ** 15 15 GND GND 16 16 H_X16_SL1_RXP0 ** NOT TESTED ** 17 17 H_X16_SL1_RXN0 ** NOT TESTED ** 18 18 GND GND 19 19 NC_2045 ** NOT TESTED ** 20 20 GND GND 21 21 H_X16_SL1_RXP1 ** NOT TESTED ** 22 22 H_X16_SL1_RXN1 ** NOT TESTED ** 23 23 GND GND 24 24 GND GND 25 25 H_X16_SL1_RXP2 ** NOT TESTED ** 26 26 H_X16_SL1_RXN2 ** NOT TESTED ** 27 27 GND GND 28 28 GND GND 29 29 H_X16_SL1_RXP3 ** NOT TESTED ** 30 30 H_X16_SL1_RXN3 ** NOT TESTED ** 31 31 GND GND 32 32 NC_2046 ** NOT TESTED ** 33 33 NC_2047 ** NOT TESTED ** 34 34 GND GND 35 35 H_X16_SL1_RXP4 ** NOT TESTED ** 36 36 H_X16_SL1_RXN4 ** NOT TESTED ** 37 37 GND GND 38 38 GND GND 39 39 H_X16_SL1_RXP5 ** NOT TESTED ** 40 40 H_X16_SL1_RXN5 ** NOT TESTED ** 41 41 GND GND 42 42 GND GND 43 43 H_X16_SL1_RXP6 ** NOT TESTED ** 44 44 H_X16_SL1_RXN6 ** NOT TESTED ** 45 45 GND GND 46 46 GND GND 47 47 H_X16_SL1_RXP7 ** NOT TESTED ** 48 48 H_X16_SL1_RXN7 ** NOT TESTED ** 49 49 GND GND 50 50 NC_2048 ** NOT TESTED ** 51 51 GND GND 52 52 H_X16_SL1_RXP8 ** NOT TESTED ** 53 53 H_X16_SL1_RXN8 ** NOT TESTED ** 54 54 GND GND 55 55 GND GND 56 56 H_X16_SL1_RXP9 ** NOT TESTED ** 57 57 H_X16_SL1_RXN9 ** NOT TESTED ** 58 58 GND GND 59 59 GND GND 60 60 H_X16_SL1_RXP10 ** NOT TESTED ** 61 61 H_X16_SL1_RXN10 ** NOT TESTED ** 62 62 GND GND 63 63 GND GND 64 64 H_X16_SL1_RXP11 ** NOT TESTED ** 65 65 H_X16_SL1_RXN11 ** NOT TESTED ** 66 66 GND GND 67 67 GND GND 68 68 H_X16_SL1_RXP12 ** NOT TESTED ** 69 69 H_X16_SL1_RXN12 ** NOT TESTED ** 70 70 GND GND 71 71 GND GND 72 72 H_X16_SL1_RXP13 ** NOT TESTED ** 73 73 H_X16_SL1_RXN13 ** NOT TESTED ** 74 74 GND GND 75 75 GND GND 76 76 H_X16_SL1_RXP14 ** NOT TESTED ** 77 77 H_X16_SL1_RXN14 ** NOT TESTED ** 78 78 GND GND 79 79 GND GND 80 80 H_X16_SL1_RXP15 ** NOT TESTED ** 81 81 H_X16_SL1_RXN15 ** NOT TESTED ** 82 82 GND GND 83 83 +12V ** NOT TESTED ** 84 84 +12V ** NOT TESTED ** 85 85 +12V ** NOT TESTED ** 86 86 GND GND 87 87 S_SMBCLK_SLOT ** NOT TESTED ** 88 88 S_SMBDATA_SLOT ** NOT TESTED ** 89 89 GND GND 90 90 +3V_ATX ** NOT TESTED ** 91 91 NC_2049 ** NOT TESTED ** 92 92 +3VSB ** NOT TESTED ** 93 93 S_WAKE_ ** NOT TESTED ** 94 94 NC_2050 ** NOT TESTED ** 95 95 GND GND 96 96 H_X16_SL1_TXP0_C ** NOT TESTED ** 97 97 H_X16_SL1_TXN0_C ** NOT TESTED ** 98 98 GND GND 99 99 PCIEX16_SL1_PRSNT_ ** NOT TESTED ** 100 100 GND GND 101 101 H_X16_SL1_TXP1_C ** NOT TESTED ** 102 102 H_X16_SL1_TXN1_C ** NOT TESTED ** 103 103 GND GND 104 104 GND GND 105 105 H_X16_SL1_TXP2_C ** NOT TESTED ** 106 106 H_X16_SL1_TXN2_C ** NOT TESTED ** 107 107 GND GND 108 108 GND GND 109 109 H_X16_SL1_TXP3_C ** NOT TESTED ** 110 110 H_X16_SL1_TXN3_C ** NOT TESTED ** 111 111 GND GND 112 112 NC_2051 ** NOT TESTED ** 113 113 PCIEX16_SL1_PRSNT_ ** NOT TESTED ** 114 114 GND GND 115 115 H_X16_SL1_TXP4_C ** NOT TESTED ** 116 116 H_X16_SL1_TXN4_C ** NOT TESTED ** 117 117 GND GND 118 118 GND GND 119 119 H_X16_SL1_TXP5_C ** NOT TESTED ** 120 120 H_X16_SL1_TXN5_C ** NOT TESTED ** 121 121 GND GND 122 122 GND GND 123 123 H_X16_SL1_TXP6_C ** NOT TESTED ** 124 124 H_X16_SL1_TXN6_C ** NOT TESTED ** 125 125 GND GND 126 126 GND GND 127 127 H_X16_SL1_TXP7_C ** NOT TESTED ** 128 128 H_X16_SL1_TXN7_C ** NOT TESTED ** 129 129 GND GND 130 130 PCIEX16_SL1_PRSNT_ ** NOT TESTED ** 131 131 GND GND 132 132 H_X16_SL1_TXP8_C ** NOT TESTED ** 133 133 H_X16_SL1_TXN8_C ** NOT TESTED ** 134 134 GND GND 135 135 GND GND 136 136 H_X16_SL1_TXP9_C ** NOT TESTED ** 137 137 H_X16_SL1_TXN9_C ** NOT TESTED ** 138 138 GND GND 139 139 GND GND 140 140 H_X16_SL1_TXP10_C ** NOT TESTED ** 141 141 H_X16_SL1_TXN10_C ** NOT TESTED ** 142 142 GND GND 143 143 GND GND 144 144 H_X16_SL1_TXP11_C ** NOT TESTED ** 145 145 H_X16_SL1_TXN11_C ** NOT TESTED ** 146 146 GND GND 147 147 GND GND 148 148 H_X16_SL1_TXP12_C ** NOT TESTED ** 149 149 H_X16_SL1_TXN12_C ** NOT TESTED ** 150 150 GND GND 151 151 GND GND 152 152 H_X16_SL1_TXP13_C ** NOT TESTED ** 153 153 H_X16_SL1_TXN13_C ** NOT TESTED ** 154 154 GND GND 155 155 GND GND 156 156 H_X16_SL1_TXP14_C ** NOT TESTED ** 157 157 H_X16_SL1_TXN14_C ** NOT TESTED ** 158 158 GND GND 159 159 GND GND 160 160 H_X16_SL1_TXP15_C ** NOT TESTED ** 161 161 H_X16_SL1_TXN15_C ** NOT TESTED ** 162 162 GND GND 163 163 PCIEX16_SL1_PRSNT_ ** NOT TESTED ** 164 164 NC_2052 ** NOT TESTED ** 165 165 NC_2053 NC 166 166 NC_2054 NC _____________________________________________________________________________________________________________________________________________________ Totals 69 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 0.0 Testable Pins = 95 UnTested Pins = 95 Analog Coverage = 0.0 Analog Tested Pins = 0 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #28 UPEX2 Loc:A2 Side:T TotalPin:101 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 GND GND 2 2 +12V ** NOT TESTED ** 3 3 +12V ** NOT TESTED ** 4 4 GND GND 5 5 NC_2072 ** NOT TESTED ** 6 6 NC_2073 ** NOT TESTED ** 7 7 NC_2074 ** NOT TESTED ** 8 8 NC_2075 ** NOT TESTED ** 9 9 +3V_ATX ** NOT TESTED ** 10 10 +3V_ATX ** NOT TESTED ** 11 11 O_X16_RST_ ** NOT TESTED ** 12 12 GND GND 13 13 CK_100M_X16SL3P ** NOT TESTED ** 14 14 CK_100M_X16SL3N ** NOT TESTED ** 15 15 GND GND 16 16 S_X16_SL3_RXP0 ** NOT TESTED ** 17 17 S_X16_SL3_RXN0 ** NOT TESTED ** 18 18 GND GND 19 19 NC_2076 ** NOT TESTED ** 20 20 GND GND 21 21 S_X16_SL3_RXP1 ** NOT TESTED ** 22 22 S_X16_SL3_RXN1 ** NOT TESTED ** 23 23 GND GND 24 24 GND GND 25 25 S_X16_SL3_RXP2 ** NOT TESTED ** 26 26 S_X16_SL3_RXN2 ** NOT TESTED ** 27 27 GND GND 28 28 GND GND 29 29 S_X16_SL3_RXP3 ** NOT TESTED ** 30 30 S_X16_SL3_RXN3 ** NOT TESTED ** 31 31 GND GND 32 32 NC_2077 ** NOT TESTED ** 33 33 NC_2078 ** NOT TESTED ** 34 34 GND GND 35 35 NC_2079 ** NOT TESTED ** 36 36 NC_2080 ** NOT TESTED ** 37 37 GND GND 38 38 GND GND 39 39 NC_2081 ** NOT TESTED ** 40 40 NC_2082 ** NOT TESTED ** 41 41 GND GND 42 42 GND GND 43 43 NC_2083 ** NOT TESTED ** 44 44 NC_2084 ** NOT TESTED ** 45 45 GND GND 46 46 GND GND 47 47 NC_2085 ** NOT TESTED ** 48 48 NC_2086 ** NOT TESTED ** 49 49 GND GND 50 50 +12V ** NOT TESTED ** 51 51 +12V ** NOT TESTED ** 52 52 +12V ** NOT TESTED ** 53 53 GND GND 54 54 S_SMBCLK_SLOT ** NOT TESTED ** 55 55 S_SMBDATA_SLOT ** NOT TESTED ** 56 56 GND GND 57 57 +3V_ATX ** NOT TESTED ** 58 58 NC_2087 ** NOT TESTED ** 59 59 +3VSB ** NOT TESTED ** 60 60 S_WAKE_ ** NOT TESTED ** 61 61 NC_2088 ** NOT TESTED ** 62 62 GND GND 63 63 S_X16_SL3_TXP0_C ** NOT TESTED ** 64 64 S_X16_SL3_TXN0_C ** NOT TESTED ** 65 65 GND GND 66 66 PCIEX16_SL3_PRSNT_ ** NOT TESTED ** 67 67 GND GND 68 68 S_X16_SL3_TXP1_C ** NOT TESTED ** 69 69 S_X16_SL3_TXN1_C ** NOT TESTED ** 70 70 GND GND 71 71 GND GND 72 72 S_X16_SL3_TXP2_C ** NOT TESTED ** 73 73 S_X16_SL3_TXN2_C ** NOT TESTED ** 74 74 GND GND 75 75 GND GND 76 76 S_X16_SL3_TXP3_C ** NOT TESTED ** 77 77 S_X16_SL3_TXN3_C ** NOT TESTED ** 78 78 GND GND 79 79 NC_2089 ** NOT TESTED ** 80 80 PCIEX16_SL3_PRSNT_ ** NOT TESTED ** 81 81 GND GND 82 82 NC_2090 ** NOT TESTED ** 83 83 NC_2091 ** NOT TESTED ** 84 84 GND GND 85 85 GND GND 86 86 NC_2092 ** NOT TESTED ** 87 87 NC_2093 ** NOT TESTED ** 88 88 GND GND 89 89 GND GND 90 90 NC_2094 ** NOT TESTED ** 91 91 NC_2095 ** NOT TESTED ** 92 92 GND GND 93 93 GND GND 94 94 NC_2096 ** NOT TESTED ** 95 95 NC_2097 ** NOT TESTED ** 96 96 GND GND 97 97 PCIEX16_SL3_PRSNT_ ** NOT TESTED ** 98 98 GND GND 99 99 PCIEX16_SL3_PRSNT_ ** NOT TESTED ** 100 100 NC_2098 NC 101 101 NC_2099 NC _____________________________________________________________________________________________________________________________________________________ Totals 38 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 0.0 Testable Pins = 61 UnTested Pins = 61 Analog Coverage = 0.0 Analog Tested Pins = 0 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #29 UPCX1 Loc:B2 Side:T TotalPin:38 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 GND GND 2 2 +12V ** NOT TESTED ** 3 3 +12V ** NOT TESTED ** 4 4 GND GND 5 5 NC_2032 ** NOT TESTED ** 6 6 NC_2033 ** NOT TESTED ** 7 7 NC_2034 ** NOT TESTED ** 8 8 NC_2035 ** NOT TESTED ** 9 9 +3V_ATX ** NOT TESTED ** 10 10 +3V_ATX ** NOT TESTED ** 11 11 O_X1_RST_ ** NOT TESTED ** 12 12 GND GND 13 13 CK_100M_X1SL1P ** NOT TESTED ** 14 14 CK_100M_X1SL1N ** NOT TESTED ** 15 15 GND GND 16 16 S_X1_SL1_RXP ** NOT TESTED ** 17 17 S_X1_SL1_RXN ** NOT TESTED ** 18 18 GND GND 19 19 +12V ** NOT TESTED ** 20 20 +12V ** NOT TESTED ** 21 21 +12V ** NOT TESTED ** 22 22 GND GND 23 23 S_SMBCLK_SLOT ** NOT TESTED ** 24 24 S_SMBDATA_SLOT ** NOT TESTED ** 25 25 GND GND 26 26 +3V_ATX ** NOT TESTED ** 27 27 NC_2036 ** NOT TESTED ** 28 28 +3VSB ** NOT TESTED ** 29 29 S_WAKE_ ** NOT TESTED ** 30 30 NC_2037 ** NOT TESTED ** 31 31 GND GND 32 32 S_X1_SL1_TXP_C ** NOT TESTED ** 33 33 S_X1_SL1_TXN_C ** NOT TESTED ** 34 34 GND GND 35 35 PCIEX1_SL1_PRSNT_ ** NOT TESTED ** 36 36 GND GND 37 37 NC_2038 NC 38 38 NC_2039 NC _____________________________________________________________________________________________________________________________________________________ Totals 10 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 0.0 Testable Pins = 26 UnTested Pins = 26 Analog Coverage = 0.0 Analog Tested Pins = 0 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #30 UP101 Loc:F3 Side:T TotalPin:57 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 P_VCORE_IOUT_R_10 X 2 2 P_VCORE_EN_10 X 3 3 P_SVID_DATA X 4 4 P_SVID_ALERT_ X 5 5 P_SVID_CLK X 6 6 P_VRM_PGD_10 X 7 7 P_VCORE_VCC5_20 ** NOT TESTED ** 8 8 P_VCORE_VRSHDN_10 X 9 9 P_VCORE_VRMP_10 X 10 10 P_VCORE_VRHOT__10 X 11 11 P_SMB_DATA_4 X 12 12 P_SMB_CLK_4 X 13 13 P_GT_IOUTA_R_10 X 14 14 P_GT_VSNA_10 X 15 15 H_GT_VCC_SENSE X 16 16 P_GT_DIFFA_10 X 17 17 P_GT_FBA_10 X 18 18 P_GT_COMPA_10 X 19 19 P_GT_CSCOMPA_10 X 20 20 P_GT_ILIMA_10 X 21 21 P_GT_CSSUMA_10 X 22 22 P_GT_CSREFA_10 ** NOT TESTED ** 23 23 P_GT_CSP1A_10 X 24 24 P_GT_CSN1A_10 ** NOT TESTED ** 25 25 P_GT_CSP2A_10 X 26 26 P_GT_CSN2A_10 ** NOT TESTED ** 27 27 P_GT_TMA_10 X 28 28 P_GT_PWM1A_10 X 29 29 P_GT_PWM2A_10 X 30 30 P_VCORE_DRON_10 X 31 31 P_VCORE_SM_ADDR_10 X 32 32 P_VCORE_PWM3_10 X 33 33 P_VCORE_PWM2_10 X 34 34 P_VCORE_PWM1_10 X 35 35 P_VCORE_TM_10 X 36 36 P_VCORE_CSN1_10 ** NOT TESTED ** 37 37 P_VCORE_CSP1_10 X 38 38 P_VCORE_CSN2_10 ** NOT TESTED ** 39 39 P_VCORE_CSP2_10 X 40 40 P_VCORE_CSN3_10 ** NOT TESTED ** 41 41 P_VCORE_CSP3_10 X 42 42 NC_1823 NC 43 43 P_VCORE_CSP4_10 X 44 44 P_VCORE_CSREF_10 ** NOT TESTED ** 45 45 P_VCORE_CSSUM_10 X 46 46 P_VCORE_ILIM_10 X 47 47 P_VCORE_CSCOMP_10 X 48 48 P_VCORE_COMP_10 X 49 49 P_VCORE_FB_10 X 50 50 P_VCORE_DIFF_10 X 51 51 H_VCC_SENSE X 52 52 P_VCORE_VSN_10 X 53 53 DGND GND 54 54 DGND GND 55 55 DGND GND 56 56 DGND GND 57 57 DGND GND _____________________________________________________________________________________________________________________________________________________ Totals 5 1 43 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 84.3 Testable Pins = 51 UnTested Pins = 8 Analog Coverage = 84.3 Analog Tested Pins = 43 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #31 UP102 Loc:F2 Side:T TotalPin:11 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 P_VCORE_PWM1_10 ** NOT TESTED ** 2 2 GND GND 3 3 P_OD_1_10 ** NOT TESTED ** 4 4 P_VCORE_VCC1_R_20 VCC 5 5 P_VCORE_LG1_20 X 6 6 P_VCORE_PHASE1_20 ** NOT TESTED ** 7 7 P_VCORE_HG1_20 X 8 8 P_VCORE_BST1_20 X 9 9 GND GND 10 10 GND GND 11 11 GND GND _____________________________________________________________________________________________________________________________________________________ Totals 5 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 50.0 Testable Pins = 6 UnTested Pins = 3 Analog Coverage = 50.0 Analog Tested Pins = 3 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #32 UP103 Loc:F2 Side:T TotalPin:11 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 P_VCORE_PWM2_10 ** NOT TESTED ** 2 2 GND GND 3 3 P_OD_2_10 ** NOT TESTED ** 4 4 P_VCORE_VCC2_R_20 VCC 5 5 P_VCORE_LG2_20 X 6 6 P_VCORE_PHASE2_20 ** NOT TESTED ** 7 7 P_VCORE_HG2_20 X 8 8 P_VCORE_BST2_20 X 9 9 GND GND 10 10 GND GND 11 11 GND GND _____________________________________________________________________________________________________________________________________________________ Totals 5 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 50.0 Testable Pins = 6 UnTested Pins = 3 Analog Coverage = 50.0 Analog Tested Pins = 3 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #33 UP104 Loc:F2 Side:T TotalPin:11 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 P_VCORE_PWM3_10 ** NOT TESTED ** 2 2 GND GND 3 3 P_OD_3_10 ** NOT TESTED ** 4 4 P_VCORE_VCC3_R_20 VCC 5 5 P_VCORE_LG3_20 X 6 6 P_VCORE_PHASE3_20 ** NOT TESTED ** 7 7 P_VCORE_HG3_20 X 8 8 P_VCORE_BST3_20 X 9 9 GND GND 10 10 GND GND 11 11 GND GND _____________________________________________________________________________________________________________________________________________________ Totals 5 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 50.0 Testable Pins = 6 UnTested Pins = 3 Analog Coverage = 50.0 Analog Tested Pins = 3 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #34 UP201 Loc:F3 Side:T TotalPin:11 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 P_GT_PWM1A_10 ** NOT TESTED ** 2 2 GND GND 3 3 P_GT_OD_1_10 ** NOT TESTED ** 4 4 P_GT_VCC1_R_20 VCC 5 5 P_GT_LG1_20 X 6 6 P_GT_PHASE1_20 ** NOT TESTED ** 7 7 P_GT_R_HG1_20 X 8 8 P_GT_BST1_20 X 9 9 GND GND 10 10 GND GND 11 11 GND GND _____________________________________________________________________________________________________________________________________________________ Totals 5 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 50.0 Testable Pins = 6 UnTested Pins = 3 Analog Coverage = 50.0 Analog Tested Pins = 3 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #35 UP202 Loc:F2 Side:T TotalPin:11 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 P_GT_PWM2A_10 ** NOT TESTED ** 2 2 GND GND 3 3 P_GT_OD_2_10 ** NOT TESTED ** 4 4 P_GT_VCC2_R_20 VCC 5 5 P_GT_LG2_20 X 6 6 P_GT_PHASE2_20 ** NOT TESTED ** 7 7 P_GT_R_HG2_20 X 8 8 P_GT_BST2_20 X 9 9 GND GND 10 10 GND GND 11 11 GND GND _____________________________________________________________________________________________________________________________________________________ Totals 5 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 50.0 Testable Pins = 6 UnTested Pins = 3 Analog Coverage = 50.0 Analog Tested Pins = 3 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #36 UP302 Loc:C3 Side:T TotalPin:8 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 P_VCCIO_OUT1_2_1_10 ** NOT TESTED ** 2 2 P_VCCIO_IN1_2_1-_10 ** NOT TESTED ** 3 3 P_VCCIO_IN1_2_1+_10 ** NOT TESTED ** 4 4 GND GND 5 5 P_VCCIO_IN_2+_10 ** NOT TESTED ** 6 6 P_VCCIO_IN_2-_10 ** NOT TESTED ** 7 7 P_VCCIO_OUT_2_10 ** NOT TESTED ** 8 8 +12V VCC _____________________________________________________________________________________________________________________________________________________ Totals 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 0.0 Testable Pins = 6 UnTested Pins = 6 Analog Coverage = 0.0 Analog Tested Pins = 0 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #37 UP501 Loc:F4 Side:T TotalPin:13 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 P_VDDQ_BOOT_20 X 2 2 P_VDDQ_UGATE_20 X 3 3 P_VDDQ_PHASE_20 ** NOT TESTED ** 4 4 P_VDDQ_LGATE_20 X 5 5 P_VDDQ_VCC_20 VCC 6 6 P_VDDQ_FB_10 X 7 7 P_VDDQ_COMP_10 X 8 8 P_+VDDQ_PG1_10 X 9 9 P_VDDQ_OFS_10 X 10 10 P_VDDQ_REFOUT_10 X 11 11 GND GND 12 12 GND GND 13 13 GND GND _____________________________________________________________________________________________________________________________________________________ Totals 4 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 88.9 Testable Pins = 9 UnTested Pins = 1 Analog Coverage = 88.9 Analog Tested Pins = 8 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #38 UP503 Loc:C4 Side:T TotalPin:13 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 P_VTT_DDR_REFIN_10 X 2 2 VDDQ ** NOT TESTED ** 3 3 VTT_DDR VCC 4 4 GND GND 5 5 P_VTT_DDR_VOSNS_10 ** NOT TESTED ** 6 6 P_VTT_DDR_REOUT_10 X 7 7 P_VTT_DDR_EN_10 X 8 8 GND GND 9 9 NC_1824 NC 10 10 P_VTT_DDR_CTRL_10 ** NOT TESTED ** 11 11 GND GND 12 12 GND GND 13 13 GND GND _____________________________________________________________________________________________________________________________________________________ Totals 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 50.0 Testable Pins = 6 UnTested Pins = 3 Analog Coverage = 50.0 Analog Tested Pins = 3 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #39 UP701 Loc:A4 Side:T TotalPin:13 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 P_+1_0V_A_EN_10 ** NOT TESTED ** 2 2 N28559643 ** NOT TESTED ** 3 3 +1_8V_A ** NOT TESTED ** 4 4 +1_8V_A ** NOT TESTED ** 5 5 +1_8V_A ** NOT TESTED ** 6 6 +5VSB VCC 7 7 +5VSB VCC 8 8 +5VSB VCC 9 9 P_1_8V_A_EN_10 ** NOT TESTED ** 10 10 P_1_8V_A__CTRL_10 ** NOT TESTED ** 11 11 GND GND 12 12 GND GND 13 13 GND GND _____________________________________________________________________________________________________________________________________________________ Totals 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 0.0 Testable Pins = 7 UnTested Pins = 7 Analog Coverage = 0.0 Analog Tested Pins = 0 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #40 UP704 Loc:B4 Side:T TotalPin:16 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 P_1_0A_L+5VSB_S VCC 2 2 GND GND 3 3 P_+1_0V_A_LP__10 ** NOT TESTED ** 4 4 P_+1_0V_A_PG_10 X 5 5 GND GND 6 6 GND GND 7 7 P_+1_0V_A_VOUT_10 GND* 8 8 P_+1_0V_A_SW_20 GND* 9 9 P_+1_0V_A_SW_20 GND* 10 10 P_+1_0V_A_BST_20 X 11 11 +1_0V_A_VCC_20 ** NOT TESTED ** 12 12 P_+1_0V_A_FB_10 X 13 13 P_+1_0V_A_EN_10 X 14 14 GND GND 15 15 P_+1_0V_A_SW_20 GND* 16 16 P_+1_0V_A_SW_20 GND* _____________________________________________________________________________________________________________________________________________________ Totals 10 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 66.7 Testable Pins = 6 UnTested Pins = 2 Analog Coverage = 66.7 Analog Tested Pins = 4 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #41 UP705 Loc:B4 Side:T TotalPin:8 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 +5VDUAL VCC 2 2 P_OV1_ADD_10 X 3 3 GND GND 4 4 S_SMBDATA_VSB ** NOT TESTED ** 5 5 S_SMBCLK_VSB ** NOT TESTED ** 6 6 P_+VCCSA_3933_OV_10 X 7 7 P_+VDDQ_3933_OV_10 ** NOT TESTED ** 8 8 P_+VCCIO_3933_OV_10 X _____________________________________________________________________________________________________________________________________________________ Totals 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 50.0 Testable Pins = 6 UnTested Pins = 3 Analog Coverage = 50.0 Analog Tested Pins = 3 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #42 UP706 Loc:D2 Side:T TotalPin:13 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 P_VCCSA_BOOT_20 X 2 2 P_VCCSA_UGATE_20 X 3 3 P_VCCSA_PHASE_20 ** NOT TESTED ** 4 4 P_VCCSA_LGATE_20 X 5 5 P_VCCSA_VCC_20 VCC 6 6 P_VCCSA_FB_10 ** NOT TESTED ** 7 7 P_VCCSA_COMP_10 X 8 8 P_VCCSA_POK_10 X 9 9 P_VCCSA_OFS_10 X 10 10 P_VCCSA_REFOUT_10 X 11 11 GND GND 12 12 GND GND 13 13 GND GND _____________________________________________________________________________________________________________________________________________________ Totals 4 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 77.8 Testable Pins = 9 UnTested Pins = 2 Analog Coverage = 77.8 Analog Tested Pins = 7 Digital Coverage = 0.0 Digital Tested Pins = 0 ____________________________________________________________________________________________________________________________________________ #43 USU1 Loc:B3 Side:T TotalPin:837 Comment: ANALOG TESTS DIGITAL TESTS STUCK FAULT TESTS ____________________ ___________________________________________ _____________________________ Pin# Grid NetName PWR/NOTEST NC CD TJ MDA STT VM PAT TTL MEM OBP I2C BS TPG TREE CLK Drives Senses Stuck Fault _____________________________________________________________________________________________________________________________________________________ 1 1 GND GND 2 2 GND GND 3 3 GND GND 4 4 S_24M_OUT X 5 5 S_24M_IN X 6 6 S_U3RXDP1 X 7 7 S_U3RXDP3 X 8 8 S_U3TXDP2_C ** NOT TESTED ** 9 9 S_U3TXDN4_C ** NOT TESTED ** 10 10 NC_2200 NC 11 11 GND GND 12 12 NC_2201 NC 13 13 S_X16_SL3_TXP1 ** NOT TESTED ** 14 14 GND GND 15 15 H_DMI_RXP1 ** NOT TESTED ** 16 16 H_DMI_RXP3 ** NOT TESTED ** 17 17 GND GND 18 18 S_X1_LAN1_TXP ** NOT TESTED ** 19 19 GND GND 20 20 S_SATA6_TXP3 ** NOT TESTED ** 21 21 S_SATA6_TXP4 ** NOT TESTED ** 22 22 S_SATA6_TXN4 ** NOT TESTED ** 23 23 GND GND 24 24 +1_0V_A_VCCAMPHYPLL GND* 25 25 GND GND 26 26 GND GND 27 27 GND GND 28 28 GND GND 29 29 GND GND 30 30 S_U3RXDN1 X 31 31 S_U3RXDP2 X 32 32 S_U3RXDN3 X 33 33 S_U3TXDP1_C ** NOT TESTED ** 34 34 S_U3TXDN2_C ** NOT TESTED ** 35 35 S_U3TXDP4_C ** NOT TESTED ** 36 36 S_U3TXDN5_C ** NOT TESTED ** 37 37 S_U3TXDN6_C ** NOT TESTED ** 38 38 NC_2231 NC 39 39 S_PCIE_RCOMPN X 40 40 NC_2232 NC 41 41 NC_2233 NC 42 42 NC_2234 NC 43 43 S_X16_SL3_TXN1 ** NOT TESTED ** 44 44 S_X16_SL3_TXP2 ** NOT TESTED ** 45 45 S_X16_SL3_TXP3 ** NOT TESTED ** 46 46 GND GND 47 47 H_DMI_RXP0 ** NOT TESTED ** 48 48 H_DMI_RXN1 ** NOT TESTED ** 49 49 H_DMI_RXN2 ** NOT TESTED ** 50 50 H_DMI_RXN3 ** NOT TESTED ** 51 51 S_X1_SL1_TXP ** NOT TESTED ** 52 52 S_X1_U3IC1_TXP ** NOT TESTED ** 53 53 S_X1_EPCI_TXP ** NOT TESTED ** 54 54 S_X1_LAN1_TXN ** NOT TESTED ** 55 55 S_SATA6_TXP1 ** NOT TESTED ** 56 56 GND GND 57 57 S_SATA6_TXN2 ** NOT TESTED ** 58 58 S_SATA6_TXN3 ** NOT TESTED ** 59 59 GND GND 60 60 +1_0V_A_VCCAMPHYPLL GND* 61 61 GND GND 62 62 GND GND 63 63 GND GND 64 64 GND GND 65 65 GND GND 66 66 S_U3RXDN2 X 67 67 GND GND 68 68 S_U3TXDN1_C ** NOT TESTED ** 69 69 S_U3TXDN3_C ** NOT TESTED ** 70 70 S_U3TXDP5_C ** NOT TESTED ** 71 71 S_U3TXDP6_C ** NOT TESTED ** 72 72 S_PCIE_RCOMPP X 73 73 NC_2240 NC 74 74 NC_2241 NC 75 75 S_X16_SL3_TXP0 ** NOT TESTED ** 76 76 S_X16_SL3_TXN2 ** NOT TESTED ** 77 77 S_X16_SL3_TXN3 ** NOT TESTED ** 78 78 H_DMI_RXN0 ** NOT TESTED ** 79 79 GND GND 80 80 H_DMI_RXP2 ** NOT TESTED ** 81 81 S_X1_SL1_TXN ** NOT TESTED ** 82 82 S_X1_U3IC1_TXN ** NOT TESTED ** 83 83 S_X1_EPCI_TXN ** NOT TESTED ** 84 84 S_SATA6_TXN1 ** NOT TESTED ** 85 85 GND GND 86 86 S_SATA6_TXP2 ** NOT TESTED ** 87 87 GND GND 88 88 +1_0V_A_VCCMIPIPLL GND* 89 89 +1_0V_A_VCCMIPIPLL GND* 90 90 GND GND 91 91 NC_2242 NC 92 92 NC_2243 NC 93 93 NC_2244 NC 94 94 NC_2245 NC 95 95 GND GND 96 96 GND GND 97 97 S_U3TXDP3_C ** NOT TESTED ** 98 98 GND GND 99 99 GND GND 100 100 GND GND 101 101 GND GND 102 102 GND GND 103 103 S_X16_SL3_TXN0 ** NOT TESTED ** 104 104 GND GND 105 105 GND GND 106 106 GND GND 107 107 GND GND 108 108 GND GND 109 109 GND GND 110 110 GND GND 111 111 GND GND 112 112 GND GND 113 113 S_SATA6_RXN2 ** NOT TESTED ** 114 114 S_SATA6_RXN4 ** NOT TESTED ** 115 115 GND GND 116 116 S_XCLK_BIASREF X 117 117 NC_2246 NC 118 118 NC_2247 NC 119 119 S_U3RXDN4 X 120 120 GND GND 121 121 GND GND 122 122 NC_2248 NC 123 123 NC_2249 NC 124 124 S_X16_SL3_RXP1 X 125 125 H_DMI_TXN1 ** NOT TESTED ** 126 126 H_DMI_TXP2 ** NOT TESTED ** 127 127 S_X1_U3IC1_RXP ** NOT TESTED ** 128 128 GND GND 129 129 GND GND 130 130 S_SATA6_RXP1 ** NOT TESTED ** 131 131 S_SATA6_RXP2 ** NOT TESTED ** 132 132 S_SATA6_RXP3 ** NOT TESTED ** 133 133 S_SATA6_RXP4 ** NOT TESTED ** 134 134 S_SATA6_TXN5 ** NOT TESTED ** 135 135 CK_24M_NSCCCLKN ** NOT TESTED ** 136 136 NC_2250 NC 137 137 GND GND 138 138 S_SATA6_RXN3 ** NOT TESTED ** 139 139 GND GND 140 140 S_SATA6_TXP5 ** NOT TESTED ** 141 141 CK_24M_NSCCCLKP ** NOT TESTED ** 142 142 CK_100M_PCHOP ** NOT TESTED ** 143 143 NC_2251 NC 144 144 GND GND 145 145 S_U3RXDP4 X 146 146 S_U3RXDN5_R ** NOT TESTED ** 147 147 NC_2252 NC 148 148 NC_2253 NC 149 149 NC_2254 NC 150 150 S_X16_SL3_RXN1 X 151 151 H_DMI_TXP1 ** NOT TESTED ** 152 152 H_DMI_TXN2 ** NOT TESTED ** 153 153 S_X1_U3IC1_RXN ** NOT TESTED ** 154 154 S_X1_SL1_RXN X 155 155 S_X1_LAN1_RXN ** NOT TESTED ** 156 156 S_SATA6_RXN1 ** NOT TESTED ** 157 157 S_SATA6_RXP6 ** NOT TESTED ** 158 158 GND GND 159 159 S_SATA6_TXP6 ** NOT TESTED ** 160 160 S_SATA6_TXN6 ** NOT TESTED ** 161 161 CK_100M_PCHON ** NOT TESTED ** 162 162 GND GND 163 163 S_U3RXDP5_R ** NOT TESTED ** 164 164 NC_2255 NC 165 165 GND GND 166 166 GND GND 167 167 GND GND 168 168 GND GND 169 169 GND GND 170 170 GND GND 171 171 S_X1_SL1_RXP X 172 172 S_X1_LAN1_RXP ** NOT TESTED ** 173 173 GND GND 174 174 S_SATA6_RXP5 ** NOT TESTED ** 175 175 S_SATA6_RXN5 ** NOT TESTED ** 176 176 NC_2256 NC 177 177 NC_2257 NC 178 178 CK_100M_PCIBCLKN ** NOT TESTED ** 179 179 CK_100M_PCIBCLKP ** NOT TESTED ** 180 180 GND GND 181 181 GND GND 182 182 GND GND 183 183 GND GND 184 184 GND GND 185 185 GND GND 186 186 NC_2258 NC 187 187 +1_0V_A_XCLK_BIAS GND* 188 188 +1_0V_A_XCLK_BIAS GND* 189 189 GND GND 190 190 GND GND 191 191 S_U3RXDP6_R ** NOT TESTED ** 192 192 S_U3RXDN6_R ** NOT TESTED ** 193 193 NC_2259 NC 194 194 S_X16_SL3_RXN0 X 195 195 S_X16_SL3_RXP2 X 196 196 S_X16_SL3_RXN3 X 197 197 GND GND 198 198 H_DMI_TXP3 ** NOT TESTED ** 199 199 S_X1_EPCI_RXP ** NOT TESTED ** 200 200 GND GND 201 201 GND GND 202 202 S_SATA6_RXN6 ** NOT TESTED ** 203 203 GND GND 204 204 GND GND 205 205 NC_2260 NC 206 206 C_CPU_XDP_ X 207 207 C_CPU_XDP X 208 208 GND GND 209 209 CK_100M_U3IC1P ** NOT TESTED ** 210 210 CK_100M_U3IC1N ** NOT TESTED ** 211 211 GND GND 212 212 GND GND 213 213 GND GND 214 214 GND GND 215 215 NC_2261 NC 216 216 S_X16_SL3_RXP0 X 217 217 S_X16_SL3_RXN2 X 218 218 S_X16_SL3_RXP3 X 219 219 H_DMI_TXN0 ** NOT TESTED ** 220 220 H_DMI_TXN3 ** NOT TESTED ** 221 221 S_X1_EPCI_RXN ** NOT TESTED ** 222 222 NC_2262 NC 223 223 NC_2263 NC 224 224 GND GND 225 225 NC_2264 NC 226 226 NC_2265 NC 227 227 GND GND 228 228 GND GND 229 229 NC_2266 NC 230 230 S_GPP_G19 X 231 231 NC_2267 NC 232 232 NC_2268 NC 233 233 GND GND 234 234 GND GND 235 235 NC_2269 NC 236 236 NC_2270 NC 237 237 GND GND 238 238 GND GND 239 239 +1_0V_A GND* 240 240 GND GND 241 241 GND GND 242 242 GND GND 243 243 H_DMI_TXP0 ** NOT TESTED ** 244 244 TP_PCH_N29 X 245 245 TP_PCH_N31 X 246 246 GND GND 247 247 GND GND 248 248 NC_2271 NC 249 249 NC_2272 NC 250 250 GND GND 251 251 NC_2273 NC 252 252 S_GPP_G18 X 253 253 NC_2274 NC 254 254 CK_100M_X1SL1N X 255 255 CK_100M_EPCIP ** NOT TESTED ** 256 256 CK_100M_EPCIN ** NOT TESTED ** 257 257 GND GND 258 258 GND GND 259 259 GND GND 260 260 TP_PCH_P24 X 261 261 TP_PCH_P27 X 262 262 TP_PCH_P29 X 263 263 TP_PCH_P31 X 264 264 NC_2275 NC 265 265 NC_2276 NC 266 266 GND GND 267 267 CK_100M_X1SL1P X 268 268 CK_100M_X16SL1N ** NOT TESTED ** 269 269 CK_100M_X16SL1P X 270 270 GND GND 271 271 CK_100M_LAN1P ** NOT TESTED ** 272 272 CK_100M_LAN1N ** NOT TESTED ** 273 273 GND GND 274 274 NC_2277 NC 275 275 NC_2278 NC 276 276 GND GND 277 277 +1_0V_A GND* 278 278 +1_0V_A GND* 279 279 GND GND 280 280 TP_PCH_R24 X 281 281 TP_PCH_R27 X 282 282 GND GND 283 283 GND GND 284 284 NC_2279 NC 285 285 NC_2280 NC 286 286 GND GND 287 287 S_GPP_G12 X 288 288 N23567070 X 289 289 N23567093 X 290 290 NC_2281 NC 291 291 NC_2282 NC 292 292 GND GND 293 293 GND GND 294 294 GND GND 295 295 GND GND 296 296 NC_2283 NC 297 297 NC_2284 NC 298 298 NC_2285 NC 299 299 NC_2286 NC 300 300 GND GND 301 301 NC_2287 NC 302 302 NC_2288 NC 303 303 GND GND 304 304 GND GND 305 305 GND GND 306 306 TP_PCH_U13 X 307 307 GND GND 308 308 GND GND 309 309 GND GND 310 310 GND GND 311 311 +1_0V_A GND* 312 312 +1_0V_A GND* 313 313 +1_0V_A GND* 314 314 +1_0V_A GND* 315 315 +1_0V_A GND* 316 316 GND GND 317 317 GND GND 318 318 GND GND 319 319 GND GND 320 320 GND GND 321 321 NC_2289 NC 322 322 NC_2290 NC 323 323 GND GND 324 324 NC_2291 NC 325 325 NC_2292 NC 326 326 GPP_G1 X 327 327 GPP_G0 X 328 328 NC_2293 NC 329 329 NC_2294 NC 330 330 GND GND 331 331 +1_0V_A GND* 332 332 GND GND 333 333 GND GND 334 334 GND GND 335 335 GND GND 336 336 GND GND 337 337 +1_0V_A GND* 338 338 +1_0V_A GND* 339 339 GND GND 340 340 NC_2295 NC 341 341 GND GND 342 342 S_USB_PN10 X 343 343 S_USB_PP10 X 344 344 GND GND 345 345 NC_2296 NC 346 346 GND GND 347 347 CK_100M_X16SL3N ** NOT TESTED ** 348 348 CK_100M_X16SL3P X 349 349 TP_PCH_W13 X 350 350 GND GND 351 351 +3VSB_ADV ** NOT TESTED ** 352 352 GND GND 353 353 GND GND 354 354 GND GND 355 355 NC_2297 NC 356 356 NC_2298 NC 357 357 GND GND 358 358 NC_2299 NC 359 359 NC_2300 NC 360 360 S_USB2_OCB_7 X 361 361 S_USB3_OC_6 ** NOT TESTED ** 362 362 NC_2301 NC 363 363 GND GND 364 364 GND GND 365 365 GND GND 366 366 GND GND 367 367 +1_0V_A GND* 368 368 +1_0V_A GND* 369 369 GND GND 370 370 GND GND 371 371 GND GND 372 372 S_USB_OC_1112 X 373 373 S_USB_OC_910 X 374 374 H_SKTOCC__R X 375 375 S_USB_PN8 X 376 376 S_USB_PP8 X 377 377 GND GND 378 378 GND GND 379 379 GND GND 380 380 GND GND 381 381 GND GND 382 382 +1_0V_A GND* 383 383 GND GND 384 384 +1_0V_A GND* 385 385 +1_0V_A GND* 386 386 GND GND 387 387 GND GND 388 388 GP_SIO_LED_SW3 X 389 389 GP_SIO_LED_SW2 X 390 390 S_USB_PP6 X 391 391 S_USB_PN6 X 392 392 GND GND 393 393 GND GND 394 394 GND GND 395 395 GND GND 396 396 CPU_VSS_AB10 GND* 397 397 CPU_VSS_AB11 GND* 398 398 N98444264 X 399 399 GND GND 400 400 GND GND 401 401 GND GND 402 402 GND GND 403 403 1083_CORE_PWR_EN X 404 404 GP_SIO_LED_SW1 X 405 405 NC_2202 NC 406 406 GND GND 407 407 NC_2203 NC 408 408 NC_2204 NC 409 409 S_GPP_F6 X 410 410 NC_2205 NC 411 411 NC_2206 NC 412 412 GND GND 413 413 S_U2DN5_R ** NOT TESTED ** 414 414 S_U2DP5_R ** NOT TESTED ** 415 415 +1_0V_A GND* 416 416 GND GND 417 417 GND GND 418 418 GND GND 419 419 +1_0V_A GND* 420 420 GND GND 421 421 +1_0V_A GND* 422 422 +1_0V_A GND* 423 423 GND GND 424 424 NC_2207 NC 425 425 S_USB_OC_78 X 426 426 GND GND 427 427 S_USB_PP11 X 428 428 S_USB_PN11 X 429 429 GND GND 430 430 S_U2DN2 X 431 431 S_U2DP2 X 432 432 GND GND 433 433 N96817948 X 434 434 GND GND 435 435 +3V ** NOT TESTED ** 436 436 GND GND 437 437 +1_0V_A GND* 438 438 NC_2208 NC 439 439 GND GND 440 440 GND GND 441 441 NC_2209 NC 442 442 GND GND 443 443 NC_2210 NC 444 444 S_USB3_OC_5 X 445 445 VCCP_GPP ** NOT TESTED ** 446 446 S_USB3_OC_34 X 447 447 S_USB3_OC_12 X 448 448 S_SATALED__R X 449 449 S_U2DN4 X 450 450 S_U2DP4 X 451 451 GND GND 452 452 NC_2211 NC 453 453 GND GND 454 454 GND GND 455 455 GND GND 456 456 +1_0V_A GND* 457 457 GND GND 458 458 +1_0V_A GND* 459 459 GND GND 460 460 GND GND 461 461 GND GND 462 462 S_GPP_E7 X 463 463 NC_2212 NC 464 464 S_U2DN6_R ** NOT TESTED ** 465 465 S_U2DP6_R ** NOT TESTED ** 466 466 S_U2DN1 X 467 467 NC_2213 NC 468 468 GND GND 469 469 GND GND 470 470 GND GND 471 471 GND GND 472 472 GND GND 473 473 GND GND 474 474 GND GND 475 475 GND GND 476 476 S_GPP_E3 X 477 477 N96817951 X 478 478 S_USB2_COMP ** NOT TESTED ** 479 479 GND GND 480 480 S_U2DP1 X 481 481 S_U2DN3 X 482 482 S_U2DP3 X 483 483 GND GND 484 484 GND GND 485 485 NC_2214 NC 486 486 NC_2215 NC 487 487 GND GND 488 488 GND GND 489 489 GND GND 490 490 NC_2216 NC 491 491 NC_2217 NC 492 492 GND GND 493 493 NC_2218 NC 494 494 S_GPP_E4 X 495 495 NC_2219 NC 496 496 S_GPP_D21 X 497 497 GND GND 498 498 H_PM_DOWN X 499 499 GND GND 500 500 GND GND 501 501 GND GND 502 502 GND GND 503 503 GND GND 504 504 GND GND 505 505 GND GND 506 506 GND GND 507 507 GND GND 508 508 S_GPP_D22 X 509 509 S_GPP_D20 X 510 510 GND GND 511 511 S_VCORE_SHDN__10_R X 512 512 S_PM_SYNC_R X 513 513 +1_0V_A_VCCAPLL GND* 514 514 S_USB_PP9 X 515 515 S_USB_PN9 X 516 516 GND GND 517 517 NC_2220 NC 518 518 NC_2221 NC 519 519 GND GND 520 520 GND GND 521 521 GND GND 522 522 GND GND 523 523 +1_0V_A GND* 524 524 +1_0V_A GND* 525 525 +1_0V_A GND* 526 526 +1_0V_A GND* 527 527 GND GND 528 528 GND GND 529 529 GND GND 530 530 GND GND 531 531 GND GND 532 532 S_GPP_D5 X 533 533 S_GPP_D19 X 534 534 GND GND 535 535 S_GPP_D18 X 536 536 GP_TYPEC_CC_DETECT_2 X 537 537 VCCP_GPP ** NOT TESTED ** 538 538 S_GPP_D17 X 539 539 S_GPP_D16 X 540 540 S_GPP_D23 X 541 541 H_CPU_TRIGGER X 542 542 H_CPURST_ X 543 543 GND GND 544 544 GND GND 545 545 S_GPP_D14 X 546 546 S_GPP_D13 X 547 547 S_CPU_TRIGGER_R X 548 548 N100473140 X 549 549 GND GND 550 550 +1_0V_A_VCCAPLL GND* 551 551 S_USB_PP7 X 552 552 S_USB_PN7 X 553 553 GND GND 554 554 GND GND 555 555 GND GND 556 556 GND GND 557 557 GND GND 558 558 +P1V0_PRIME_PCH_FUSE_2V8 GND* 559 559 GND GND 560 560 S_GPP_B1 X 561 561 GND GND 562 562 GND GND 563 563 GND GND 564 564 GP_TYPEC_CC_DETECT_1 X 565 565 O2_HW_SEL X 566 566 GND GND 567 567 S_GPP_D0 X 568 568 VCCP_GPP ** NOT TESTED ** 569 569 S_GPP_D8 X 570 570 S_GPP_D15 X 571 571 O2_VCO_SEL X 572 572 S_HDA_SDO X 573 573 S_HDA_SCLK_R X 574 574 S_CPUPWRGD_R X 575 575 GND GND 576 576 GND GND 577 577 GND GND 578 578 GND GND 579 579 GND GND 580 580 GND GND 581 581 GND GND 582 582 S_GPP_D6 X 583 583 U3E1_SMI__VSB X 584 584 GND GND 585 585 H_HDA_SDI X 586 586 S_JTAG_TCK X 587 587 GND GND 588 588 VCCP_GPP ** NOT TESTED ** 589 589 GND GND 590 590 GND GND 591 591 GND GND 592 592 GND GND 593 593 S_SUSCLK X 594 594 NC_2222 NC 595 595 +1_0V_A_VCCAPLL GND* 596 596 GND GND 597 597 S_GPP_B11 X 598 598 GND GND 599 599 TP_PCH_AN29 X 600 600 GND GND 601 601 S_GPP_D1 X 602 602 O_PME_ X 603 603 GND GND 604 604 S_GPP_D3 X 605 605 S_GPP_D7 X 606 606 S_GPP_C23 X 607 607 GP_TYPEC_PWR_CTL X 608 608 S_JTAG_TDO X 609 609 S_JTAG_TDI X 610 610 GND GND 611 611 GND GND 612 612 S_JTAG_TMS X 613 613 S_JTAGX X 614 614 GND GND 615 615 GND GND 616 616 GND GND 617 617 L1_ISOLATE_ ** NOT TESTED ** 618 618 S_GPP_A16 X 619 619 NC_2223 NC 620 620 TP_PCH_AR22 X 621 621 S_GPP_B15 X 622 622 NC_2224 NC 623 623 S_GPP_B21 X 624 624 S_GPP_H1 X 625 625 GND GND 626 626 GND GND 627 627 S_GPP_C17 X 628 628 S_GPP_C21 X 629 629 S_GPP_C19 X 630 630 GND GND 631 631 S_GPP_C18 X 632 632 S_GPP_C20 X 633 633 S_ITP_PMODE X 634 634 S_XDP_PREQ_ X 635 635 S_XDP_PRDY_ X 636 636 GND GND 637 637 GND GND 638 638 O_IOPWRBTN_ ** NOT TESTED ** 639 639 GND GND 640 640 O_KBRST_ X 641 641 S_LAD2 ** NOT TESTED ** 642 642 S_LAD0 ** NOT TESTED ** 643 643 S_GPP_B7 X 644 644 S_GPP_B23 X 645 645 S_GPP_B22 X 646 646 NC_2225 NC 647 647 CLKREQ__LAN1 ** NOT TESTED ** 648 648 GND GND 649 649 S_GPP_C16 X 650 650 S_GPP_C13 X 651 651 S_GPP_C14 X 652 652 GND GND 653 653 GND GND 654 654 GND GND 655 655 GND GND 656 656 GND GND 657 657 S_GPP_C15 X 658 658 ME_UNLOCK ** NOT TESTED ** 659 659 S_GPP_C11 X 660 660 GND GND 661 661 NC_2226 NC 662 662 NC_2227 NC 663 663 NC_2228 NC 664 664 GND GND 665 665 S_DPWROK ** NOT TESTED ** 666 666 S_SLP_WLAN_ X 667 667 S_SLP_LAN_ X 668 668 GND GND 669 669 CK_24M_TPM_R X 670 670 S_LAD1 ** NOT TESTED ** 671 671 GND GND 672 672 GND GND 673 673 S_GPP_B20 X 674 674 GND GND 675 675 GND GND 676 676 S_GPP_C10 X 677 677 S_GPP_C9 X 678 678 O_RSTCON_ ** NOT TESTED ** 679 679 NC_2229 NC 680 680 S_DVI_HPD X 681 681 GND GND 682 682 S_PWROK X 683 683 GND GND 684 684 S_SLP_S3_ X 685 685 S_GPP_A7 X 686 686 GND GND 687 687 S_CLKRUN_ X 688 688 S_GPP_B6 X 689 689 GP_CHAFAN_PWM_DC_ X 690 690 GND GND 691 691 NC_2230 NC 692 692 S_GPP_H7 X 693 693 S_GPP_H11 X 694 694 GND GND 695 695 S_GPP_C6 X 696 696 S_SMBCLK_VSB ** NOT TESTED ** 697 697 S_GPP_C7 X 698 698 S_SYSPWROK X 699 699 S_HDMI_HPD ** NOT TESTED ** 700 700 S_XDP_TRST_ X 701 701 GND GND 702 702 L1_SMBCLK X 703 703 GND GND 704 704 GND GND 705 705 S_DP2VGA_HPD ** NOT TESTED ** 706 706 S_DVI_DDC_CLK X 707 707 S_HD_BITCLK_R ** NOT TESTED ** 708 708 S_RSMRST_ ** NOT TESTED ** 709 709 S_SLP_S5_ X 710 710 +3VSB_HDA ** NOT TESTED ** 711 711 S_SERIRQ ** NOT TESTED ** 712 712 +3VSB ** NOT TESTED ** 713 713 +3V_BAT ** NOT TESTED ** 714 714 +3VSB_ADV ** NOT TESTED ** 715 715 VCC_RTCEXT_CAP X 716 716 +1V0_PCH_VCCDSW X 717 717 VCCPGPPA ** NOT TESTED ** 718 718 S_GPP_H6 X 719 719 S_GPP_H14 X 720 720 S_GPP_C5 X 721 721 S_GPP_C8 X 722 722 VCCPGPPD ** NOT TESTED ** 723 723 GND GND 724 724 S_HDMI_DDC_CLK ** NOT TESTED ** 725 725 S_HD_SDOUT_R ** NOT TESTED ** 726 726 S_SRTCRST_ X 727 727 GND GND 728 728 S_SLP_SUS_ X 729 729 S_GP_D1 X 730 730 GND GND 731 731 S_SX_EXIT_HOLDOFF_ X 732 732 S_SUSACK_ X 733 733 GND GND 734 734 S_GPP_A18 X 735 735 S_GPP_B9 X 736 736 GND GND 737 737 S_PLTRST__R ** NOT TESTED ** 738 738 S_SPI_MOSI ** NOT TESTED ** 739 739 GND GND 740 740 S_GPP_H4 X 741 741 PCIEX1_SL1_PRSNT_ X 742 742 GND GND 743 743 S_GPP_H15 X 744 744 O2_RELATCH X 745 745 L1_SMBDATA X 746 746 S_GPP_C2 X 747 747 S_SMBDATA_VSB ** NOT TESTED ** 748 748 VCCPGPPD ** NOT TESTED ** 749 749 GND GND 750 750 GND GND 751 751 S_DVI_DDC_DATA X 752 752 NC_2235 NC 753 753 S_RTCX1 X 754 754 S_RTCRST_ X 755 755 S_WAKE_ X 756 756 S_D4_RESET_ X 757 757 S_SLP_A_ X 758 758 CK_24M_SIO_R X 759 759 S_PWRDWN_ X 760 760 S_GPP_A17 X 761 761 S_GPP_A23 X 762 762 S_GPP_B3 X 763 763 S_GPP_B5 X 764 764 S_SLP_S0_ X 765 765 GP_CHAFAN_PWM_DC_2 X 766 766 S_SPI_IO2 ** NOT TESTED ** 767 767 S_SPI_CLK ** NOT TESTED ** 768 768 S_GPP_H3 X 769 769 PCIEX16_SL1_PRSNT_ X 770 770 S_GPP_H13 X 771 771 S_GPP_H18 X 772 772 O2_PWR_EN X 773 773 +3VSB ** NOT TESTED ** 774 774 VCCPGPPD ** NOT TESTED ** 775 775 VCCPGPPD ** NOT TESTED ** 776 776 NC_2236 NC 777 777 GND GND 778 778 VCCPFUSE_3P3 ** NOT TESTED ** 779 779 S_HDMI_DDC_DATA ** NOT TESTED ** 780 780 S_GPP_I4 X 781 781 S_HD_RST__R ** NOT TESTED ** 782 782 S_HD_SYNC_R ** NOT TESTED ** 783 783 S_RTCX2 X 784 784 L1_LAN_WAKE_ X 785 785 S_GP_D0 X 786 786 S_GP_D7 X 787 787 S_SLP_S4_ X 788 788 S_LAD3 ** NOT TESTED ** 789 789 S_PME_ ** NOT TESTED ** 790 790 S_GPP_A22 X 791 791 S_SUSWARN_ X 792 792 S_GPP_A19 X 793 793 S_GPP_A20 X 794 794 S_VR_ALERT_ X 795 795 S_GPP_B4 X 796 796 S_GPP_B8 X 797 797 S_SPKR X 798 798 S_GPP_B17 X 799 799 S_GPP_B18 X 800 800 S_SPI_IO3 ** NOT TESTED ** 801 801 S_SPI_CS0_ ** NOT TESTED ** 802 802 PCIEX16_SL3_PRSNT_ X 803 803 S_GPP_H9 X 804 804 S_GPP_H10 X 805 805 S_GPP_H12 X 806 806 S_GPP_H23 X 807 807 O2_ADFC_1 X 808 808 S_GPP_H16 X 809 809 +3VSB ** NOT TESTED ** 810 810 GND GND 811 811 GND GND 812 812 GND GND 813 813 NC_2237 NC 814 814 VCCPFUSE_3P3 ** NOT TESTED ** 815 815 VCCPFUSE_3P3 ** NOT TESTED ** 816 816 NC_2238 NC 817 817 NC_2239 NC 818 818 A_HD_SDIN0 ** NOT TESTED ** 819 819 GND GND 820 820 S_INTRUDER_ X 821 821 GND GND 822 822 S_LFRAME_ ** NOT TESTED ** 823 823 GND GND 824 824 S_GPP_A21 X 825 825 GND GND 826 826 S_GPP_B10 X 827 827 GND GND 828 828 S_SPI_MISO ** NOT TESTED ** 829 829 GND GND 830 830 S_GPP_H17 X 831 831 GND GND 832 832 O2_ADFC_2 X 833 833 GND GND 834 834 +3V_SPI ** NOT TESTED ** 835 835 +3V_SPI ** NOT TESTED ** 836 836 +3V_SPI ** NOT TESTED ** 837 837 GND GND _____________________________________________________________________________________________________________________________________________________ Totals 340 102 242 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Coverage = 61.3 Testable Pins = 395 UnTested Pins = 153 Analog Coverage = 61.3 Analog Tested Pins = 242 Digital Coverage = 0.0 Digital Tested Pins = 0